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may 2003 1394 host controller solutions data manual slls521a designing with this device may require extensive support. before incorporating this device into a design, customers should contact ti or an authorized ti distributor. note
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 description 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 1 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 related documents 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 trademarks 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 ordering information 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 terminal descriptions 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TSB43AB21A 1394 ohci controller programming model 3?1 . . . . . . . . . . . . 3.1 pci configuration registers 3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 vendor id register 3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 device id register 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 command register 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 status register 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 class code and revision id register 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 latency timer and class cache line size register 3 ? 6 . . . . . . . . . . . . . . 3.8 header type and bist register 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 ohci base address register 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 ti extension base address register 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 cardbus cis base address register 3 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 cardbus cis pointer register 3 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 subsystem identification register 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 power management capabilities pointer register 3 ? 11 . . . . . . . . . . . . . . . 3.15 interrupt line and pin register 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 min_gnt and max_lat register 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17 ohci control register 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18 capability id and next item pointer registers 3 ? 13 . . . . . . . . . . . . . . . . . . . 3.19 power management capabilities register 3 ? 14 . . . . . . . . . . . . . . . . . . . . . . 3.20 power management control and status register 3 ? 15 . . . . . . . . . . . . . . . . 3.21 power management extension registers 3 ? 15 . . . . . . . . . . . . . . . . . . . . . . . 3.22 pci phy control register 3 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 miscellaneous configuration register 3 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24 link enhancement control register 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.25 subsystem access register 3 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.26 gpio control register 3 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ohci registers 4?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 ohci version register 4 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 guid rom register 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 4.3 asynchronous transmit retries register 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . 4.4 csr data register 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 csr compare register 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 csr control register 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 configuration rom header register 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 bus identification register 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 bus options register 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 guid high register 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 guid low register 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 configuration rom mapping register 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 posted write address low register 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 posted write address high register 4 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 vendor id register 4 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 host controller control register 4 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 self-id buffer pointer register 4 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 self-id count register 4 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 isochronous receive channel mask high register 4 ? 16 . . . . . . . . . . . . . . 4.20 isochronous receive channel mask low register 4 ? 17 . . . . . . . . . . . . . . . 4.21 interrupt event register 4 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 interrupt mask register 4 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 isochronous transmit interrupt event register 4 ? 22 . . . . . . . . . . . . . . . . . . 4.24 isochronous transmit interrupt mask register 4 ? 23 . . . . . . . . . . . . . . . . . . . 4.25 isochronous receive interrupt event register 4 ? 23 . . . . . . . . . . . . . . . . . . . 4.26 isochronous receive interrupt mask register 4 ? 24 . . . . . . . . . . . . . . . . . . . 4.27 initial bandwidth available register 4 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 initial channels available high register 4 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . 4.29 initial channels available low register 4 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 fairness control register 4 ? 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 link control register 4 ? 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 node identification register 4 ? 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 phy layer control register 4 ? 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34 isochronous cycle timer register 4 ? 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 asynchronous request filter high register 4 ? 31 . . . . . . . . . . . . . . . . . . . . . 4.36 asynchronous request filter low register 4 ? 33 . . . . . . . . . . . . . . . . . . . . . 4.37 physical request filter high register 4 ? 34 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.38 physical request filter low register 4 ? 36 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.39 physical upper bound register (optional register) 4 ? 36 . . . . . . . . . . . . . . 4.40 asynchronous context control register 4 ? 37 . . . . . . . . . . . . . . . . . . . . . . . . 4.41 asynchronous context command pointer register 4 ? 38 . . . . . . . . . . . . . . 4.42 isochronous transmit context control register 4 ? 39 . . . . . . . . . . . . . . . . . . 4.43 isochronous transmit context command pointer register 4 ? 40 . . . . . . . . 4.44 isochronous receive context control register 4 ? 40 . . . . . . . . . . . . . . . . . . 4.45 isochronous receive context command pointer register 4 ? 42 . . . . . . . . 4.46 isochronous receive context match register 4 ? 43 . . . . . . . . . . . . . . . . . . .
v 5 ti extension registers 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 dv and mpeg2 timestamp enhancements 5 ? 1 . . . . . . . . . . . . . . . . . . . . . 5.2 isochronous receive digital video enhancements 5 ? 2 . . . . . . . . . . . . . . . 5.3 isochronous receive digital video enhancements register 5 ? 2 . . . . . . . 5.4 link enhancement register 5 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 timestamp offset register 5 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial eeprom interface 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 phy register configuration 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 base registers 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 port status register 7 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 vendor identification register 7 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 vendor-dependent register 7 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 power-class programming 7 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 application information 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 phy port cable connection 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 crystal selection 8 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 bus reset 8 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 emi guidelines 8 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical characteristics 9 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 absolute maximum ratings over operating temperature ranges 9 ? 1 . 9.2 recommended operating conditions 9 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 electrical characteristics over recommended operating conditions 9 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 electrical characteristics over recommended ranges of operating conditions 9 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 device 9 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 driver 9 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 receiver 9 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 thermal characteristics 9 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 switching characteristics for phy port interface 9 ? 5 . . . . . . . . . . . . . . . . . 9.7 operating, timing, and switching characteristics of xi 9 ? 5 . . . . . . . . . . . 9.8 switching characteristics for pci interface 9 ? 5 . . . . . . . . . . . . . . . . . . . . . . 9.8.1 cardbus pc card clock specifications 9 ? 6 . . . . . . . . . . . . . . . . 9.8.2 3.3-v timing parameters 9 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mechanical information 10 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi list of illustrations figure title page 2 ? 1 TSB43AB21A terminal assignments 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 TSB43AB21A block diagram 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ? 1 tp cable connections 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ? 2 typical compliant dc isolated outer shield termination 8 ? 2 . . . . . . . . . . . . . 8 ? 3 non-dc isolated outer shield termination 8 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . 8 ? 4 load capacitance for the TSB43AB21A phy 8 ? 3 . . . . . . . . . . . . . . . . . . . . . . . 8 ? 5 recommended crystal and capacitor layout 8 ? 3 . . . . . . . . . . . . . . . . . . . . . . . 9 ? 1 test load diagram 9 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ? 2 cardbus pc card clock waveform 9 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table title page 2 ? 1 signals sorted by terminal number 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 signal names sorted alphanumerically to terminal number 2 ? 4 . . . . . . . . . . 2 ? 3 pci system terminals 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 pci address and data terminals 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 pci interface control terminals 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 miscellaneous terminals 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 physical layer terminals 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 power supply terminals 2 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 bit field access tag descriptions 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 pci configuration register map 3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 command register description 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 status register description 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 class code and revision id register description 3 ? 6 . . . . . . . . . . . . . . . . . . . 3 ? 6 latency timer and class cache line size register description 3 ? 6 . . . . . . . 3 ? 7 header type and bist register description 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 ohci base address register description 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 ti base address register description 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 cardbus cis base address register description 3 ? 9 . . . . . . . . . . . . . . . . . . . 3 ? 11 cardbus cis pointer register description 3 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 subsystem identification register description 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 interrupt line and pin registers description 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . .
vii 3 ? 14 min_gnt and max_lat register description 3 ? 12 . . . . . . . . . . . . . . . . . . . . . 3 ? 15 ohci control register description 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 16 capability id and next item pointer registers description 3 ? 13 . . . . . . . . . . . . 3 ? 17 power management capabilities register description 3 ? 14 . . . . . . . . . . . . . . . 3 ? 18 power management control and status register description 3 ? 15 . . . . . . . . . 3 ? 19 power management extension registers description 3 ? 15 . . . . . . . . . . . . . . . . 3 ? 20 pci phy control register 3 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 21 miscellaneous configuration register 3 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 22 link enhancement control register description 3 ? 18 . . . . . . . . . . . . . . . . . . . . 3 ? 23 subsystem access register description 3 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 24 general-purpose input/output control register description 3 ? 20 . . . . . . . . . . 4 ? 1 ohci register map 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 ohci version register description 4 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 guid rom register description 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 asynchronous transmit retries register description 4 ? 6 . . . . . . . . . . . . . . . . 4 ? 5 csr control register description 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 6 configuration rom header register description 4 ? 8 . . . . . . . . . . . . . . . . . . . . 4 ? 7 bus options register description 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 8 configuration rom mapping register description 4 ? 11 . . . . . . . . . . . . . . . . . . . 4 ? 9 posted write address low register description 4 ? 11 . . . . . . . . . . . . . . . . . . . . 4 ? 10 posted write address high register description 4 ? 12 . . . . . . . . . . . . . . . . . . . . 4 ? 11 host controller control register description 4 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 12 self-id count register description 4 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 13 isochronous receive channel mask high register description 4 ? 16 . . . . . . . 4 ? 14 isochronous receive channel mask low register description 4 ? 17 . . . . . . . . 4 ? 15 interrupt event register description 4 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 16 interrupt mask register description 4 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 17 isochronous transmit interrupt event register description 4 ? 22 . . . . . . . . . . . 4 ? 18 isochronous receive interrupt event register description 4 ? 23 . . . . . . . . . . . 4 ? 19 initial bandwidth available register description 4 ? 24 . . . . . . . . . . . . . . . . . . . . . 4 ? 20 initial channels available high register description 4 ? 25 . . . . . . . . . . . . . . . . . 4 ? 21 initial channels available low register description 4 ? 25 . . . . . . . . . . . . . . . . . 4 ? 22 fairness control register description 4 ? 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 23 link control register description 4 ? 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 24 node identification register description 4 ? 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 25 phy control register description 4 ? 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 26 isochronous cycle timer register description 4 ? 30 . . . . . . . . . . . . . . . . . . . . . . 4 ? 27 asynchronous request filter high register description 4 ? 31 . . . . . . . . . . . . . 4 ? 28 asynchronous request filter low register description 4 ? 33 . . . . . . . . . . . . . . 4 ? 29 physical request filter high register description 4 ? 34 . . . . . . . . . . . . . . . . . . . 4 ? 30 physical request filter low register description 4 ? 36 . . . . . . . . . . . . . . . . . . . 4 ? 31 asynchronous context control register description 4 ? 37 . . . . . . . . . . . . . . . . . 4 ? 32 asynchronous context command pointer register description 4 ? 38 . . . . . . . 4 ? 33 isochronous transmit context control register description 4 ? 39 . . . . . . . . . .
viii 4 ? 34 isochronous receive context control register description 4 ? 40 . . . . . . . . . . . 4 ? 35 isochronous receive context match register description 4 ? 43 . . . . . . . . . . . . 5 ? 1 ti extension register map 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 isochronous receive digital video enhancements register description 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 3 link enhancement register description 5 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 4 timestamp offset register description 5 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 registers and bits loadable through serial eeprom 6 ? 1 . . . . . . . . . . . . . . . 6 ? 2 serial eeprom map 6 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 1 base register configuration 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 2 base register field descriptions 7 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 3 page 0 (port status) register configuration 7 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 4 page 0 (port status) register field descriptions 7 ? 4 . . . . . . . . . . . . . . . . . . . . 7 ? 5 page 1 (vendor id) register configuration 7 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 6 page 1 (vendor id) register field descriptions 7 ? 5 . . . . . . . . . . . . . . . . . . . . . 7 ? 7 page 7 (vendor-dependent) register configuration 7 ? 6 . . . . . . . . . . . . . . . . . 7 ? 8 page 7 (vendor-dependent) register field descriptions 7 ? 6 . . . . . . . . . . . . . 7 ? 9 power class descriptions 7 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 ? 1 1 introduction this chapter provides an overview of the texas instruments TSB43AB21A device and its features. 1.1 description the texas instruments TSB43AB21A device is an integrated 1394a-2000 ohci phy/link-layer controller (llc) device that is fully compliant with the pci local bus specification , the pci bus power management interface specification (revision 1.1), ieee std 1394-1995, ieee std 1394a-2000, and the 1394 open host controller interface specification (release 1.1). it is capable of transferring data between the 33-mhz pci bus and the 1394 bus at 100m bits/s, 200m bits/s, and 400m bits/s. the TSB43AB21A device provides one 1394 port. the TSB43AB21A device also supports the ieee std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. as required by the 1394 open host controller interface specification (ohci) and ieee std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. the pci configuration header is accessed through configuration cycles specified by pci, and it provides plug-and-play (pnp) compatibility. furthermore, the TSB43AB21A device is compliant with the pci bus power management interface specification as specified by the pc 2001 design guide requirements. the TSB43AB21A device supports the d0, d1, d2, and d3 power states. the TSB43AB21A design provides pci bus master bursting, and it is capable of transferring a cacheline of data at 132m bytes/s after connection to the memory controller. because pci latency can be large, deep fifos are provided to buffer the 1394 data. the TSB43AB21A device provides physical write posting buffers and a highly-tuned physical data path for sbp-2 performance. the TSB43AB21A device also provides multiple isochronous contexts, multiple cacheline burst transfers, and advanced internal arbitration. an advanced cmos process achieves low power consumption and allows the TSB43AB21A device to operate at pci clock rates up to 33 mhz. the TSB43AB21A phy-layer provides the digital and analog transceiver functions needed to implement a single-port node in a cable-based 1394 network. the cable port incorporates two differential line transceivers. the transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. the TSB43AB21A phy-layer requires only an external 24.576-mhz crystal as a reference for the cable ports. an external clock may be provided instead of a crystal. an internal oscillator drives an internal phase-locked loop (pll), which generates the required 393.216-mhz reference signal. this reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. a 49.152-mhz clock signal is supplied to the integrated llc for synchronization and is used for resynchronization of the received data. data bits to be transmitted through the cable port are received from the integrated llc and are latched internally in synchronization with the 49.152-mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304m, 196.608m, or 393.216m bits/s (referred to as s100, s200, or s400 speeds, respectively) as the outbound data-strobe information stream. during transmission, the encoded data information is transmitted differentially on the twisted-pair b (tpb) cable pair, and the encoded strobe information is transmitted differentially on the twisted-pair a (tpa) cable pair. during packet reception, the tpa and tpb transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa cable pair, and the encoded strobe information is received on the tpb cable pair. the received data-strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits are resynchronized to the local 49.152-mhz system clock and sent to the integrated llc. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. the outputs of these comparators are used by the internal logic to determine the
1 ? 2 arbitration status. the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage on the tpb pair for the presence of the remotely supplied twisted-pair bias voltage. the TSB43AB21A device provides a 1.86-v nominal bias voltage at the tpbias terminal for port termination. this bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. this bias voltage source must be stabilized by an external filter capacitor of 1.0 f. the line drivers in the TSB43AB21A device operate in a high-impedance current mode and are designed to work with external 112- ? line-termination resistor networks in order to match the 110- ? cable impedance. the network is composed of a pair of series-connected 56- ? resistors. the midpoint of the pair of resistors that is directly connected to the tpa terminals is connected to its corresponding tpbias voltage terminal. the midpoint of the pair of resistors that is directly connected to the tpb terminals is coupled to ground through a parallel r-c network with recommended values of 5 k ? and 220 pf. the values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. an external resistor connected between the r0 and r1 terminals sets the driver output current and other internal operating currents. this current-setting resistor has a value of 6.34 k ? 1%. when the power supply of the TSB43AB21A device is off and the twisted-pair cables are connected, the TSB43AB21A transmitter and receiver circuitry present a high impedance to the cable and do not load the tpbias voltage at the other end of the cable. when the device is in a low-power state (for example, d2 or d3) the TSB43AB21A device automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). in this low-power mode, the TSB43AB21A device disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming tpbias, for example). the lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected or disabled with the port interrupt enable bit cleared. the TSB43AB21A device exits the low-power mode when bit 19 (lps) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1 or when a port event occurs which requires that the TSB43AB21A device to become active in order to respond to the event or to notify the llc of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is detected on a nondisabled port). when the TSB43AB21A device is in the low-power mode, the internal 49.153-mhz clock becomes active (and the integrated phy layer becomes operative) within 2 ms after bit 19 (lps) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. the TSB43AB21A device supports hardware enhancements to better support digital video (dv) and mpeg data stream reception and transmission. these enhancements are enabled through the isochronous receive digital video enhancements register at ohci offset a88h (see chapter 5, ti extension registers ). the enhancements include automatic timestamp insertion for transmitted dv and mpeg-formatted streams and common isochronous packet (cip) header stripping for received dv streams. the cip format is defined by the iec 61883-1:1998 specification. the enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both dv and mpeg cip formats. the TSB43AB21A device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale ? that is, the value is less than the current cycle timer when the packet is transmitted.
1 ? 3 1.2 features the TSB43AB21A device supports the following features: ? fully compliant with 1394 open host controller interface specification (release 1.1) ? fully compliant with provisions of ieee std 1394-1995 for a high-performance serial bus ? and ieee std 1394a-2000 ? fully interoperable with firewire and i.link implementations of ieee std 1394 ? compliant with intel mobile power guideline 2000 ? full ieee std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume ? power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, pci power management for link-layer, and inactive ports powered down ? ultralow-power sleep mode ? one ieee std 1394a-2000 fully compliant cable port at 100m bits/s, 200m bits/s, or 400m bits/s ? cable port monitors line conditions for active connection to remote node ? cable power presence monitoring ? 1.8-v core logic with universal pci interfaces compatible with 3.3-v and 5-v pci signaling environments ? physical write posting of up to three outstanding transactions ? pci burst transfers and deep fifos to tolerate large host latency ? pci_clkrun protocol ? external cycle timer control for customized synchronization ? extended resume signaling for compatibility with legacy dv components ? phy-link logic performs system initialization and arbitration functions ? phy-link encode and decode functions included for data-strobe bit level encoding ? phy-link incoming data resynchronized to local clock ? low-cost 24.576-mhz crystal provides transmit and receive data at 100m bits/s, 200m bits/s, or 400m bits/s ? node power class information signaling for system power management ? serial rom interface supports 2-wire serial eeprom devices ? two general-purpose i/os ? register bits give software control of contender bit, power class bits, link active control bit, and ieee std 1394a-2000 features ? fabricated in advanced low-power cmos process ? pci and cardbus register support ? isochronous receive dual-buffer mode ? out-of-order pipelining for asynchronous transmit requests ? register access fail interrupt when the phy sclk is not active ? pci power-management d0, d1, d2, and d3 power states ? implements technology covered by one or more patents of apple computer, incorporated and sgs thompson, limited.
1 ? 4 ? initial bandwidth available and initial channels available registers ? pme support per 1394 open host controller interface specification 1.3 related documents ? 1394 open host controller interface specification (release 1.1) ? ieee standard for a high performance serial bus (ieee std 1394-1995) ? ieee standard for a high performance serial bus?amendment 1 (ieee std 1394a-2000) ? pc card standard?electrical specification ? pc 2001 design guide ? pci bus power management interface specification (revision 1.1) ? pci local bus specification (revision 2.2) ? mobile power guideline 2000 ? serial bus protocol 2 (sbp-2) ? iec 61883-1:1998 consumer audio/video equipment digital interface part 1: general 1.4 trademarks ohci-lynx and ti are trademarks of texas instruments. other trademarks are the property of their respective owners. 1.5 ordering information ordering number name voltage package TSB43AB21A iohci-lynx 3.3 v pdt TSB43AB21Ai iohci-lynx (industrial temperature) 3.3 v pdt
2 ? 1 2 terminal descriptions this section provides the terminal descriptions for the TSB43AB21A device. figure 2 ? 1 shows the signal assigned to each terminal in the package. table 2 ? 1 and table 2 ? 2 provide a cross-reference between each terminal number and the signal name on that terminal. table 2 ? 1 is arranged in terminal number order, and table 2 ? 2 lists signals in alphabetical order.
2 ? 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 101 102 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 99 100 62 30 67 TSB43AB21A integrated phy ohci-lynx 32 31 63 64 97 98 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 agnd agnd agnd nc nc nc nc nc av dd r1 r0 agnd tpbias0 tpa0+ tpa0 ? tpb0+ tpb0 ? agnd agnd agnd av dd av dd cps test0 test1 dgnd test2 test3 dv dd pc0 pc1 pc2 dgnd pci_c/be3 v ddp pci_idsel pci_ad23 pci_ad22 dv dd pci_ad21 pci_ad20 pci_ad19 pci_ad18 dgnd pci_ad17 pci_ad16 pci_c/be2 v ddp pci_frame pci_irdy dv dd pci_trdy pci_devsel pci_stop dgnd pci_perr pci_serr pci_par dv dd pci_c/be1 pci_ad15 v ddp pci_ad14 dgnd cna test8 test9 reg18 sda scl gpio2 gpio3 dv dd cyclein cycleout/cardbu s pci_rst pci_ad0 dgnd pci_ad1 pci_ad2 pci_ad3 pci_ad4 v ddp pci_ad5 pci_ad6 dgnd pci_ad7 pci_c/be0 dv dd pci_ad8 pci_ad9 pci_ad10 dgnd pci_ad11 pci_ad12 pci_ad13 av dd av dd filter0 filter1 xi xo pllv dd pll gnd reg_en test17 test16 pci_clkrun pci_inta /cint g_rst dv dd pci_clk dgnd pci_gnt pci_req v ddp p ci_pme /cstschg pci_ad31 dgnd pci_ad30 pci_ad29 pci_ad28 dv dd pci_ad27 pci_ad26 reg18 pci_ad25 pci_ad24 figure 2 ? 1. TSB43AB21A terminal assignments
2 ? 3 table 2 ? 1. signals sorted by terminal number no. terminal name no. terminal name no. terminal name no. terminal name 1 av dd 33 dgnd 65 pci_ad13 97 pc2 2 av dd 34 pci_c/be3 66 pci_ad12 98 pc1 3 filter0 35 v ddp 67 pci_ad11 99 pc0 4 filter1 36 pci_idsel 68 dgnd 100 dv dd 5 xi 37 pci_ad23 69 pci_ad10 101 test3 6 xo 38 pci_ad22 70 pci_ad9 102 test2 7 pllv dd 39 dv dd 71 pci_ad8 103 dgnd 8 pll gnd 40 pci_ad21 72 dv dd 104 test1 9 reg_en 41 pci_ad20 73 pci_c/be0 105 test0 10 test17 42 pci_ad19 74 pci_ad7 106 cps 11 test16 43 pci_ad18 75 dgnd 107 av dd 12 pci_clkrun 44 dgnd 76 pci_ad6 108 av dd 13 pci_inta /cint 45 pci_ad17 77 pci_ad5 109 agnd 14 g_rst 46 pci_ad16 78 v ddp 110 agnd 15 dv dd 47 pci_c/be2 79 pci_ad4 111 agnd 16 pci_clk 48 v ddp 80 pci_ad3 112 tpb0 ? 17 dgnd 49 pci_frame 81 pci_ad2 113 tpb0+ 18 pci_gnt 50 pci_irdy 82 pci_ad1 114 tpa0 ? 19 pci_req 51 dv dd 83 dgnd 115 tpa0+ 20 v ddp 52 pci_trdy 84 pci_ad0 116 tpbias0 21 pci_pme /cstschg 53 pci_devsel 85 pci_rst 117 agnd 22 pci_ad31 54 pci_stop 86 cycleout/cardbus 118 r0 23 dgnd 55 dgnd 87 cyclein 119 r1 24 pci_ad30 56 pci_perr 88 dv dd 120 av dd 25 pci_ad29 57 pci_serr 89 gpio3 121 nc 26 pci_ad28 58 pci_par 90 gpio2 122 nc 27 dv dd 59 dv dd 91 scl 123 nc 28 pci_ad27 60 pci_c/be1 92 sda 124 nc 29 pci_ad26 61 pci_ad15 93 reg18 125 nc 30 reg18 62 v ddp 94 test9 126 agnd 31 pci_ad25 63 pci_ad14 95 test8 127 agnd 32 pci_ad24 64 dgnd 96 cna 128 agnd
2 ? 4 table 2 ? 2. signal names sorted alphanumerically to terminal number terminal name no. terminal name no. terminal name no. terminal name no. agnd 109 dv dd 88 pci_ad17 45 pci_serr 57 agnd 110 dv dd 100 pci_ad18 43 pci_stop 54 agnd 111 filter0 3 pci_ad19 42 pci_trdy 52 agnd 117 filter1 4 pci_ad20 41 pll gnd 8 agnd 126 gpio2 90 pci_ad21 40 pllv dd 7 agnd 127 gpio3 89 pci_ad22 38 reg_en 9 agnd 128 g_rst 14 pci_ad23 37 reg18 30 av dd 1 nc 121 pci_ad24 32 reg18 93 av dd 2 nc 122 pci_ad25 31 r0 118 av dd 107 nc 123 pci_ad26 29 r1 119 av dd 108 nc 124 pci_ad27 28 scl 91 av dd 120 nc 125 pci_ad28 26 sda 92 cna 96 pc0 99 pci_ad29 25 test0 105 cps 106 pc1 98 pci_ad30 24 test1 104 cyclein 87 pc2 97 pci_ad31 22 test2 102 cycleout/cardbus 86 pci_ad0 84 pci_c/be0 73 test3 101 dgnd 17 pci_ad1 82 pci_c/be1 60 test8 95 dgnd 23 pci_ad2 81 pci_c/be2 47 test9 94 dgnd 33 pci_ad3 80 pci_c/be3 34 test16 11 dgnd 44 pci_ad4 79 pci_clk 16 test17 10 dgnd 55 pci_ad5 77 pci_clkrun 12 tpa0 ? 114 dgnd 64 pci_ad6 76 pci_devsel 53 tpa0+ 115 dgnd 68 pci_ad7 74 pci_frame 49 tpb0 ? 112 dgnd 75 pci_ad8 71 pci_gnt 18 tpb0+ 113 dgnd 83 pci_ad9 70 pci_idsel 36 tpbias0 116 dgnd 103 pci_ad10 69 pci_inta /cint 13 v ddp 20 dv dd 15 pci_ad11 67 pci_irdy 50 v ddp 35 dv dd 27 pci_ad12 66 pci_par 58 v ddp 48 dv dd 39 pci_ad13 65 pci_perr 56 v ddp 62 dv dd 51 pci_ad14 63 pci_pme /cstschg 21 v ddp 78 dv dd 59 pci_ad15 61 pci_req 19 xi 5 dv dd 72 pci_ad16 46 pci_rst 85 xo 6
2 ? 5 the terminals are grouped in tables by functionality, such as pci system function and power supply function (see table 2 ? 3 through table 2 ? 8). the terminal numbers are also listed for convenient reference. table 2 ? 3. pci system terminals terminal i/o description name no. i/o description g_rst 14 i global power reset. this reset brings all of the TSB43AB21A internal registers to their default states, including those registers not reset by pci_rst . when g_rst is asserted, the device is completely nonfunctional, placing all output buffers in a high-impedance state. when implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB43AB21A device. g_rst is designed to be a one-time power-on reset, and pci_rst must be connected to the pci bus rst . g_rst must be asserted for a minimum of 2 ms. pci_clk 16 i pci bus clock. provides timing for all transactions on the pci bus. all pci signals are sampled at the rising edge of pci_clk. pci_inta /cint 13 o interrupt signal. this output indicates interrupts from the TSB43AB21A device to the host. this terminal signals a cardbus interrupt (cint ) when cardbus (terminal 86) is tied low. pci_rst 85 i pci reset. when this bus reset is asserted, the TSB43AB21A device places all output buffers in a high-impedance state and resets all internal registers except device power management context- and vendor-specific bits initialized by host power-on software. when pci_rst is asserted, the device is completely nonfunctional. connect this terminal to pci bus rst . table 2 ? 4. pci address and data terminals terminal i/o description name no. i/o description pci_ad31 pci_ad30 pci_ad29 pci_ad28 pci_ad27 pci_ad26 pci_ad25 pci_ad24 pci_ad23 pci_ad22 pci_ad21 pci_ad20 pci_ad19 pci_ad18 pci_ad17 pci_ad16 pci_ad15 pci_ad14 pci_ad13 pci_ad12 pci_ad11 pci_ad10 pci_ad9 pci_ad8 pci_ad7 pci_ad6 pci_ad5 pci_ad4 pci_ad3 pci_ad2 pci_ad1 pci_ad0 22 24 25 26 28 29 31 32 37 38 40 41 42 43 45 46 61 63 65 66 67 69 70 71 74 76 77 79 80 81 82 84 i/o pci address/data bus. these signals make up the multiplexed pci address and data bus on the pci interface. during the address phase of a pci cycle, ad31 ? ad0 contain a 32-bit address or other destination information. during the data phase, ad31 ? ad0 contain data.
2 ? 6 table 2 ? 5. pci interface control terminals terminal i/o description name no. i/o description pci_clkrun 12 i/o clock run. this terminal provides clock control through the clkrun protocol. this terminal is implemented as open-drain and must be pulled low through a 10-k ? nominal resistor for designs where clkrun is not implemented. for mobile applications where clkrun is implemented, the pullup resistor is typically provided by the system central resource. pci_c/be0 pci_c/be1 pci_c/be2 pci_c/be3 73 60 47 34 i/o pci bus commands and byte enables. the command and byte enable signals are multiplexed on the same pci terminals. during the address phase of a bus cycle, pci_c/be3 ? pci_c/be0 define the bus command. during the data phase, this 4-bit bus is used for byte enables. pci_devsel 53 i/o pci device select. the TSB43AB21A device asserts this signal to claim a pci cycle as the target device. as a pci initiator, the TSB43AB21A device monitors this signal until a target responds. if no target responds before time-out occurs, the TSB43AB21A device terminates the cycle with an initiator abort. pci_frame 49 i/o pci cycle frame. this signal is driven by the initiator of a pci bus cycle. pci_frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when pci_frame is deasserted, the pci bus transaction is in the final data phase. pci_gnt 18 i pci bus grant. this signal is driven by the pci bus arbiter to grant the TSB43AB21A device access to the pci bus after the current data transaction has completed. this signal may or may not follow a pci bus request, depending upon the pci bus parking algorithm. pci_idsel 36 i initialization device select. pci_idsel selects the TSB43AB21A device during configuration space accesses. pci_idsel can be connected to 1 of the upper 21 pci address lines on the pci bus. pci_irdy 50 i/o pci initiator ready. pci_irdy indicates the ability of the pci bus initiator to complete the current data phase of the transaction. a data phase is completed upon a rising edge of pci_clk where both pci_irdy and pci_trdy are asserted. pci_par 58 i/o pci parity. in all pci bus read and write cycles, the TSB43AB21A device calculates even parity across the pci_ad and pci_c/be buses. as an initiator during pci cycles, the TSB43AB21A device outputs this parity indicator with a one-pci_clk delay. as a target during pci cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (pci_perr ). pci_perr 56 i/o pci parity error indicator. this signal is driven by a pci device to indicate that calculated parity does not match pci_par when bit 6 (perr_enb) is set to 1 in the command register at offset 04h in the pci configuration space (see section 3.4, command register ). pci_pme / cstschg 21 o power management event or card status change. this terminal indicates wake events to the host. when implemented in a cardbus application and cardbus is tied low, the output is the active high cstschg indication. this terminal is implemented as an open-drain output. pci_req 19 o pci bus request. asserted by the TSB43AB21A device to request access to the bus as an initiator. the host arbiter asserts pci_gnt when the TSB43AB21A device has been granted access to the bus. pci_serr 57 o pci system error. when bit 8 (serr_enb) in the command register at offset 04h in the pci configuration space (see section 3.4, command register ) is set to 1, the output is pulsed, indicating an address parity error has occurred. the TSB43AB21A device need not be the target of the pci cycle to assert this signal. this terminal is implemented as open-drain. pci_stop 54 i/o pci cycle stop signal. this signal is driven by a pci target to request the initiator to stop the current pci bus transaction. this signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers. pci_trdy 52 i/o pci target ready. pci_trdy indicates the ability of the pci bus target to complete the current data phase of the transaction. a data phase is completed upon a rising edge of pci_clk where both pci_irdy and pci_trdy are asserted.
2 ? 7 table 2 ? 6. miscellaneous terminals terminal i/o description name no. i/o description cyclein 87 i/o the cyclein terminal allows an external 8-khz clock to be used as a cycle timer for synchronization with other system devices. if this terminal is not implemented, it must be pulled high to dv dd through a pullup resistor. cycleout/ cardbus 86 i/o this terminal is sampled when g_rst is asserted and is used to select between pc card and non-pc card implementations. if cardbus is sampled low at reset, software programs an appropriate value into the cardbus cis base address register at offset 18h in the pci configuration space (see section 3.11, cardbus cis base address register ). after reset, this terminal may function as cycleout. the cycleout terminal provides an 8-khz cycle timer synchronization signal. if cycleout is not implemented, this terminal must be pulled up to dv dd through a pullup resistor. for cardbus implementations, this terminal must be tied to ground through a pulldown resistor and the pullup resistor is not needed. gpio2 90 i/o general-purpose i/o [2]. this terminal defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220- ? resistor. gpio3 89 i/o general-purpose i/o [3]. this terminal defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220- ? resistor. reg_en 9 i regulator enable. this terminal must be tied to ground to enable the internal voltage regulator. when using a single 3.3-v supply, this terminal must be tied to ground to enable the internal voltage regulator. when using a dual 1.8-v/3.3-v supply to provide power to the device, reg_en must be pulled to dv dd to disable the internal voltage regulator. scl 91 i/o serial clock. this terminal provides the serial clock signaling and is implemented as open-drain. for normal operation (a rom is implemented in the design), this terminal must be pulled high to the rom dv dd with a 2.7-k ? resistor. otherwise, it must be pulled low to ground with a 220- ? resistor. sda 92 i/o serial data. at pci_rst , the sda signal is sampled to determine if a two-wire serial rom is present. if the serial rom is detected, this terminal provides the serial data signaling. this terminal is implemented as open-drain, and for normal operation (a rom is implemented in the design), this terminal must be pulled high to the rom dv dd with a 2.7-k ? resistor. otherwise, it must be pulled low to ground with a 220- ? resistor. test17 test16 test9 test8 test3 test2 test1 test0 10 11 94 95 101 102 104 105 i/o terminals test[9, 8, 3, 2, 1, 0] are used for factory test of the TSB43AB21A device and must be connected to ground for normal operation. terminal test[17:16] must be pulled to v dd . these terminals can be pulled to v dd through a common pullup resistor.
2 ? 8 table 2 ? 7. physical layer terminals terminal type i/o description name no. type i/o description cna 96 cmos i/o cable not active. this terminal is asserted high when the port is not receiving incoming bias voltage. if not used, this terminal must be strapped either to dv dd or to gnd through a resistor. to enable the cna terminal, the bios must set bit 7 (cnaout) of the pci phy control register at offset ech in the pci configuration space (see section 3.22, pci phy control register ). if an eeprom is implemented and cna functionality is needed, bit 7 of byte offset 16h in the serial eeprom must be set. this sets the bit in the pci configuration space at power up via the eeprom. cps 106 cmos i cable power status input. this terminal is normally connected to cable power through a 400-k ? resistor. this circuit drives an internal comparator that detects the presence of cable power. if cps does not detect cable power, this terminal must be pulled to av dd . filter0 filter1 3 4 cmos i/o pll filter terminals. these terminals are connected to an external capacitance to form a lag-lead filter required for stable operation of the internal frequency multiplier pll running off of the crystal oscillator. a 0.1- f 10% capacitor is the only external component required to complete this filter. pc0 pc1 pc2 99 98 97 cmos i power class programming inputs. on hardware reset, these inputs set the default value of the power class indicated during self-id. programming is done by tying these terminals high or low. r0 r1 118 119 bias ? current-setting resistor terminals. these terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. a resistance of 6.34 k ? 1% is required to meet the ieee std 1394-1995 output voltage limits. tpa0+ tpa0 ? 115 114 cable i/o twisted-pair cable a differential signal terminals. board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. tpb0+ tpb0 ? 113 112 cable i/o twisted-pair cable b differential signal terminals. board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector. tpbias0 116 cable i/o twisted-pair bias output. this provides the 1.86-v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection. each of these pins must be decoupled with a 1.0- f capacitor to ground. xi xo 5 6 crystal ? crystal oscillator inputs. these pins connect to a 24.576-mhz parallel resonant fundamental mode crystal. the optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see section 8.2, crystal selection ). terminal 5 has an internal 10-k ? (nominal value) pulldown resistor. an external clock input can be connected to the xi terminal. when using an external clock input, the xo terminal must be left unconnected. refer to section 9.7 for the operating characteristics of the xi terminal.
2 ? 9 table 2 ? 8. power supply terminals terminal type i/o description name no. type i/o description agnd 109 ? 111, 117, 126 ? 128 supply ? analog circuit ground terminals. these terminals must be tied together to the low-impedance circuit board ground plane. av dd 1, 2, 107, 108, 120 supply ? analog circuit power terminals. a parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 f and 0.001 f. lower frequency 10- f filtering capacitors are also recommended. these supply terminals are separated from pllv dd and dv dd internal to the device to provide noise isolation. they must be tied at a low-impedance point on the circuit board. dgnd 17, 23, 33, 44, 55, 64, 68, 75, 83, 103 supply ? digital circuit ground terminals. these terminals must be tied together to the low-impedance circuit board ground plane. dv dd 15, 27, 39, 51, 59, 72, 88, 100 supply ? digital circuit power terminals. a parallel combination of high frequency decoupling capacitors near each dv dd terminal is suggested, such as 0.1 f and 0.001 f. lower frequency 10- f filtering capacitors are also recommended. these supply terminals are separated from pllv dd and av dd internal to the device to provide noise isolation. they must be tied at a low-impedance point on the circuit board. pll gnd 8 supply ? pll circuit ground terminal. this terminal must be tied to the low-impedance circuit board ground plane. pllv dd 7 supply ? pll circuit power terminal. a parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 f and 0.001 f. lower frequency 10- f filtering capacitors are also recommended. this supply terminal is separated from dv dd and av dd internal to the device to provide noise isolation. it must be tied to a low-impedance point on the circuit board. reg18 30, 93 supply ? reg18. 1.8-v power supply for the device core. if the internal voltage regulator is enabled (reg_en is tied low), these terminals must be left unconnected. the internal voltage regulator provides 1.8 v from dv dd . when the internal regulator is disabled (reg_en is high), the reg18 terminals can be used to supply an external 1.8-v supply to the TSB43AB21A core. it is recommended that 0.1- f bypass capacitors be used and placed close to these terminals. v ddp 20, 35, 48, 62, 78 supply ? pci signaling clamp voltage power input. pci signals are clamped per the pci local bus specification . in addition, if a 5-v rom is used, the v ddp must be connected to 5 v.
2 ? 10
3 ? 1 3 TSB43AB21A 1394 ohci controller programming model this section describes the internal pci configuration registers used to program the TSB43AB21A 1394 open host controller interface. all registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. a bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. table 3 ? 1 describes the field access tags. table 3 ? 1. bit field access tag descriptions access tag name meaning r read field can be read by software. w write field can be written by software to any value. s set field can be set by a write of 1. writes of 0 have no effect. c clear field can be cleared by a write of 1. writes of 0 have no effect. u update field can be autonomously updated by the TSB43AB21A device. figure 3 ? 1 shows a simplified block diagram of the TSB43AB21A device.
3 ? 2 received data decoder/retimer arbitration and control state machine logic bias voltage and current generator transmit data encoder cable port 0 crystal oscillator, pll system, and clock generator internal registers isochronous transmit contexts asynchronous transmit contexts physical dma and response pci target sm phy register access and status monitor central arbiter and pci initiator sm cycle start generator and cycle monitor synthesized bus reset receive fifo link transmit link receive pci host bus interface resp time-out request filters general request receive asynchronous response receive isochronous receive contexts ohci pci power mgmt and clkrun transmit fifo receive acknowledge serial rom gpios crc misc interface phy/ link interface figure 3 ? 1. TSB43AB21A block diagram
3 ? 3 3.1 pci configuration registers the TSB43AB21A device is a single-function pci device. the configuration header is compliant with the pci local bus specification as a standard header. table 3 ? 2 illustrates the pci configuration header that includes both the predefined portion of the configuration space and the user-definable registers. table 3 ? 2. pci configuration register map register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch ohci base address 10h ti extension base address 14h cardbus cis base address 18h reserved 1ch ? 27h cardbus cis pointer 28h subsystem id subsystem vendor id 2ch reserved 30h reserved pci power management capabilities pointer 34h reserved 38h maximum latency minimum grant interrupt pin interrupt line 3ch ohci control 40h power management capabilities next item pointer capability id 44h pm data pmcsr_bse power management control and status 48h reserved 4ch ? ebh pci phy control ech miscellaneous configuration f0h link enhancement control f4h subsystem device id alias subsystem vendor id alias f8h gpio3 gpio2 reserved fch 3.2 vendor id register the vendor id register contains a value allocated by the pci sig and identifies the manufacturer of the pci device. the vendor id assigned to texas instruments is 104ch. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id offset: 00h type: read-only default: 104ch
3 ? 4 3.3 device id register the device id register contains a value assigned to the TSB43AB21A device by texas instruments. the device identification for the TSB43AB21A device is 8026h. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 register: device id offset: 02h type: read-only default: 8026h 3.4 command register the command register provides control over the TSB43AB21A interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification , as seen in the following bit descriptions. see table 3 ? 3 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r r/w r r/w r r/w r r/w r/w r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command offset: 04h type: read/write, read-only default: 0000h table 3 ? 3. command register description bit field name type description 15 ? 10 rsvd r reserved. bits 15 ? 10 return 0s when read. 9 fbb_enb r fast back-to-back enable. the TSB43AB21A device does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 serr_enb r/w pci_serr enable. when bit 8 is set to 1, the TSB43AB21A pci_serr driver is enabled. pci_serr can be asserted after detecting an address parity error on the pci bus. 7 step_enb r address/data stepping control. the TSB43AB21A device does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 perr_enb r/w parity error enable. when bit 6 is set to 1, the TSB43AB21A device is enabled to drive pci_perr response to parity errors through the pci_perr signal. 5 vga_enb r vga palette snoop enable. the TSB43AB21A device does not feature vga palette snooping; therefore, bit 5 returns 0 when read. 4 mwi_enb r/w memory write and invalidate enable. when bit 4 is set to 1, the TSB43AB21A device is enabled to generate mwi pci bus commands. if this bit is cleared, the TSB43AB21A device generates memory write commands instead. 3 special r special cycle enable. the TSB43AB21A function does not respond to special cycle transactions; therefore, bit 3 returns 0 when read. 2 master_enb r/w bus master enable. when bit 2 is set to 1, the TSB43AB21A device is enabled to initiate cycles on the pci bus. 1 memory_enb r/w memory response enable. setting bit 1 to 1 enables the TSB43AB21A device to respond to memory cycles on the pci bus. this bit must be set to access ohci registers. 0 io_enb r i/o space enable. the TSB43AB21A device does not implement any i/o-mapped functionality; therefore, bit 0 returns 0 when read.
3 ? 5 3.5 status register the status register provides status over the TSB43AB21A interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification , as seen in the following bit descriptions. see table 3 ? 4 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type rcu rcu rcu rcu rcu r r rcu r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status offset: 06h type: read/clear/update, read-only default: 0210h table 3 ? 4. status register description bit field name type description 15 par_err rcu detected parity error. bit 15 is set to 1 when either an address parity or data parity error is detected. 14 sys_err rcu signaled system error. bit 14 is set to 1 when pci_serr is enabled and the TSB43AB21A device has signaled a system error to the host. 13 mabort rcu received master abort. bit 13 is set to 1 when a cycle initiated by the TSB43AB21A device on the pci bus has been terminated by a master abort. 12 tabort_rec rcu received target abort. bit 12 is set to 1 when a cycle initiated by the TSB43AB21A device on the pci bus was terminated by a target abort. 11 tabort_sig rcu signaled target abort. bit 11 is set to 1 by the TSB43AB21A device when it terminates a transaction on the pci bus with a target abort. 10 ? 9 pci_speed r devsel timing. bits 10 and 9 encode the timing of pci_devsel and are hardwired to 01b, indicating that the TSB43AB21A device asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 datapar rcu data parity error detected. bit 8 is set to 1 when the following conditions have been met: a. pci_perr was asserted by any pci device including the TSB43AB21A device. b. the TSB43AB21A device was the bus master during the data parity error. c. bit 6 (perr_en) in the command register at offset 04h in the pci configuration space (see section 3.4, command register ) is set to 1. 7 fbb_cap r fast back-to-back capable. the TSB43AB21A device cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 udf r user-definable features (udf) supported. the TSB43AB21A device does not support the udf; therefore, bit 6 is hardwired to 0. 5 66mhz r 66-mhz capable. the TSB43AB21A device operates at a maximum pci_clk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 caplist r capabilities list. bit 4 returns 1 when read, indicating that capabilities additional to standard pci are implemented. the linked list of pci power-management capabilities is implemented in this function. 3 ? 0 rsvd r reserved. bits 3 ? 0 return 0s when read.
3 ? 6 3.6 class code and revision id register the class code and revision id register categorizes the TSB43AB21A device as a serial bus controller (0ch), controlling an ieee 1394 bus (00h), with an ohci programming model (10h). furthermore, the ti chip revision is indicated in the least significant byte. see table 3 ? 5 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name class code and revision id type r r r r r r r r r r r r r r r r default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name class code and revision id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 register: class code and revision id offset: 08h type: read-only default: 0c00 1000h table 3 ? 5. class code and revision id register description bit field name type description 31 ? 24 baseclass r base class. this field returns 0ch when read, which broadly classifies the function as a serial bus controller. 23 ? 16 subclass r subclass. this field returns 00h when read, which specifically classifies the function as controlling an ieee 1394 serial bus. 15 ? 8 pgmif r programming interface. this field returns 10h when read, which indicates that the programming model is compliant with the 1394 open host controller interface specification . 7 ? 0 chiprev r silicon revision. this field returns 00h when read, which indicates the silicon revision of the TSB43AB21A device. 3.7 latency timer and class cache line size register the latency timer and class cache line size register is programmed by host bios to indicate system cache line size and the latency timer associated with the TSB43AB21A device. see table 3 ? 6 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name latency timer and class cache line size type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: latency timer and class cache line size offset: 0ch type: read/write default: 0000h table 3 ? 6. latency timer and class cache line size register description bit field name type description 15 ? 8 latency_timer r/w pci latency timer. the value in this register specifies the latency timer for the TSB43AB21A device, in units of pci clock cycles. when the TSB43AB21A device is a pci bus initiator and asserts pci_frame , the latency timer begins counting from zero. if the latency timer expires before the TSB43AB21A transaction has terminated, the TSB43AB21A device terminates the transaction when its pci_gnt is deasserted. 7 ? 0 cacheline_sz r/w cache line size. this value is used by the TSB43AB21A device during memory write and invalidate, memory-read line, and memory-read multiple transactions.
3 ? 7 3.8 header type and bist register the header type and built-in self-test (bist) register indicates the TSB43AB21A pci header type and no built-in self-test. see table 3 ? 7 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name header type and bist type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: header type and bist offset: 0eh type: read-only default: 0000h table 3 ? 7. header type and bist register description bit field name type description 15 ? 8 bist r built-in self-test. the TSB43AB21A device does not include a bist; therefore, this field returns 00h when read. 7 ? 0 header_type r pci header type. the TSB43AB21A device includes the standard pci header, which is communicated by returning 00h when this field is read. 3.9 ohci base address register the ohci base address register is programmed with a base address referencing the memory-mapped ohci control. when bios writes all 1s to this register, the value read back is ffff f800h, indicating that at least 2k bytes of memory address space are required for the ohci registers. see table 3 ? 8 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ohci base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ohci base address type r/w r/w r/w r/w r/w r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: ohci base address offset: 10h type: read/write, read-only default: 0000 0000h table 3 ? 8. ohci base address register description bit field name type description 31 ? 11 ohcireg_ptr r/w ohci register pointer. this field specifies the upper 21 bits of the 32-bit ohci base address register. 10 ? 4 ohci_sz r ohci register size. this field returns 0s when read, indicating that the ohci registers require a 2k-byte region of memory. 3 ohci_pf r ohci register prefetch. bit 3 returns 0 when read, indicating that the ohci registers are nonprefetchable. 2 ? 1 ohci_memtype r ohci memory type. this field returns 0s when read, indicating that the ohci base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 ohci_mem r ohci memory indicator. bit 0 returns 0 when read, indicating that the ohci registers are mapped into system memory space.
3 ? 8 3.10 ti extension base address register the ti extension base address register is programmed with a base address referencing the memory-mapped ti extension registers. when bios writes all 1s to this register, the value read back is ffff c000h, indicating that at least 16k bytes of memory address space are required for the ti registers. see table 3 ? 9 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ti extension base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ti extension base address type r/w r/w r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: ti extension base address offset: 14h type: read/write, read-only default: 0000 0000h table 3 ? 9. ti base address register description bit field name type description 31 ? 14 tireg_ptr r/w ti register pointer. this field specifies the upper 18 bits of the 32-bit ti base address register. 13 ? 4 ti_sz r ti register size. this field returns 0s when read, indicating that the ti registers require a 16k-byte region of memory. 3 ti_pf r ti register prefetch. bit 3 returns 0 when read, indicating that the ti registers are nonprefetchable. 2 ? 1 ti_memtype r ti memory type. this field returns 0s when read, indicating that the ti base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 ti_mem r ti memory indicator. bit 0 returns 0 when read, indicating that the ti registers are mapped into system memory space.
3 ? 9 3.11 cardbus cis base address register if cardbus is sampled high on a g_rst , this 32-bit register returns 0s when read. if cardbus is sampled low, this register is programmed with a base address referencing the memory-mapped card information structure (cis). this register must be programmed with a nonzero value before the cis can be accessed. see table 3 ? 10 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus cis base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus cis base address type r/w r/w r/w r/w r/w r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus cis base address offset: 18h type: read/write, read-only default: 0000 0000h table 3 ? 10. cardbus cis base address register description bit field name type description 31 ? 11 cis_base r/w cis base address. this field specifies the upper 21 bits of the 32-bit cis base address. if cardbus is sampled high on a g_rst , this field is read-only, returning 0s when read. 10 ? 4 cis_sz r cis address space size. this field returns 0s when read, indicating that the cis space requires a 2k-byte region of memory. 3 cis_pf r cis prefetch. bit 3 returns 0 when read, indicating that the cis is nonprefetchable. furthermore, the cis is a byte-accessible address space, and either a doubleword or 16-bit word access yields indeterminate results. 2 ? 1 cis_memtype r cis memory type. this field returns 0s when read, indicating that the cardbus cis base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 cis_mem r cis memory indicator. bit 0 returns 0 when read, indicating that the cis is mapped into system memory space.
3 ? 10 3.12 cardbus cis pointer register cardbus to the TSB43AB21A device is sampled at g_rst to determine the TSB43AB21A application. if cardbus is sampled high, this register is read-only returning 0s when read. if cardbus is sampled low, this register contains the pointer to the cardbus card information structure (cis). see table 3 ? 11 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus cis pointer type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus cis pointer type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus cis pointer offset: 28h type: read-only default: 0000 0000h table 3 ? 11. cardbus cis pointer register description bit field name type description 31 ? 28 rom_image r since the cis is not implemented as a rom image, this field returns 0s when read. 27 ? 3 cis_offset r this field indicates the offset into the cis address space where the cis begins, and bits 7 ? 3 are loaded from the serial eeprom field cis_offset (7 ? 3). this implementation allows the TSB43AB21A device to produce serial eeprom addresses equal to the lower pci address byte to acquire data from the serial eeprom. 2 ? 0 cis_indicator r this field indicates the address space where the cis resides and returns 011b if cardbus is sampled low at g_rst . 011b indicates that cardbus cis base address register at offset 18h in the pci configuration header contains the cis base address. if cardbus is sampled high at g_rst , this field contains 000b.
3 ? 11 3.13 subsystem identification register the subsystem identification register is used for system and option card identification purposes. this register can be initialized from the serial eeprom or programmed via the subsystem access register at offset f8h in the pci configuration space (see section 3.25, subsystem access register ). see table 3 ? 12 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name subsystem identification type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem identification type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem identification offset: 2ch type: read/update default: 0000 0000h table 3 ? 12. subsystem identification register description bit field name type description 31 ? 16 ohci_ssid ru subsystem device id. this field indicates the subsystem device id. 15 ? 0 ohci_ssvid ru subsystem vendor id. this field indicates the subsystem vendor id. 3.14 power management capabilities pointer register the power management capabilities pointer register provides a pointer into the pci configuration header where the power-management register block resides. the TSB43AB21A configuration header doublewords at offsets 44h and 48h provide the power-management registers. this register is read-only and returns 44h when read. bit 7 6 5 4 3 2 1 0 name power management capabilities pointer type r r r r r r r r default 0 1 0 0 0 1 0 0 register: power management capabilities pointer offset: 34h type: read-only default: 44h
3 ? 12 3.15 interrupt line and pin register the interrupt line and pin register communicates interrupt line routing information. see table 3 ? 13 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name interrupt line and pin type r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 register: interrupt line and pin offset: 3ch type: read/write default: 0100h table 3 ? 13. interrupt line and pin registers description bit field name type description 15 ? 8 intr_pin r interrupt pin. this field returns 01h when read, indicating that the TSB43AB21A pci function signals interrupts on the pci_inta terminal. 7 ? 0 intr_line r/w interrupt line. this field is programmed by the system and indicates to software which interrupt line the TSB43AB21A pci_inta is connected to. 3.16 min_gnt and max_lat register the min_gnt and max_lat register communicates to the system the desired setting of bits 15 ? 8 in the latency timer and class cache line size register at offset 0ch in the pci configuration space (see section 3.7, latency timer and class cache line size register ). if a serial eeprom is detected, the contents of this register are loaded through the serial eeprom interface after a g_rst . if no serial eeprom is detected, this register returns a default value that corresponds to the max_lat = 4, min_gnt = 2. see table 3 ? 14 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name min_gnt and max_lat type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 register: min_gnt and max_lat offset: 3eh type: read/update default: 0402h table 3 ? 14. min_gnt and max_lat register description bit field name type description 15 ? 8 max_lat ru maximum latency. the contents of this field may be used by host bios to assign an arbitration priority level to the TSB43AB21A device. the default for this register indicates that the TSB43AB21A device may need to access the pci bus as often as every 0.25 s; thus, an extremely high priority level is requested. the contents of this field may also be loaded through the serial eeprom. 7 ? 0 min_gnt ru minimum grant. the contents of this field may be used by host bios to assign a latency timer register value to the TSB43AB21A device. the default for this register indicates that the TSB43AB21A device may need to sustain burst transfers for nearly 64 s and thus request a large value be programmed in bits 15 ? 8 of the TSB43AB21A latency timer and class cache line size register at offset 0ch in the pci configuration space (see section 3.7, latency timer and class cache line size register ).
3 ? 13 3.17 ohci control register the pci ohci control register is defined by the 1394 open host controller interface specification and provides a bit for big endian pci support. see table 3 ? 15 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ohci control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ohci control type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: ohci control offset: 40h type: read/write, read-only default: 0000 0000h table 3 ? 15. ohci control register description bit field name type description 31 ? 1 rsvd r reserved. bits 31 ? 1 return 0s when read. 0 global_swap r/w when bit 0 is set to 1, all quadlets read from and written to the pci interface are byte-swapped (big endian). 3.18 capability id and next item pointer registers the capability id and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. see table 3 ? 16 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name capability id and next item pointer type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 register: capability id and next item pointer offset: 44h type: read-only default: 0001h table 3 ? 16. capability id and next item pointer registers description bit field name type description 15 ? 8 next_item r next item pointer. the TSB43AB21A device supports only one additional capability that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. 7 ? 0 capability_id r capability identification. this field returns 01h when read, which is the unique id assigned by the pci sig for pci power-management capability.
3 ? 14 3.19 power management capabilities register the power management capabilities register indicates the capabilities of the TSB43AB21A device related to pci power management. see table 3 ? 17 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management capabilities type ru r r r r r r r r r r r r r r r default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 register: power management capabilities offset: 46h type: read/update, read-only default: 7e02h table 3 ? 17. power management capabilities register description bit field name type description 15 pme_d3cold ru pci_pme support from d3 cold . this bit can be set to 1 or cleared to 0 via bit 15 (pme_d3cold) in the miscellaneous configuration register at offset f0h in the pci configuration space (see section 3.23, miscellaneous configuration register ). the miscellaneous configuration register is loaded from rom. when this bit is set to 1, it indicates that the TSB43AB21A device is capable of generating a pci_pme wake event from d3 cold . this bit state is dependent upon the TSB43AB21A v aux implementation and may be configured by using bit 15 (pme_d3cold) in the miscellaneous configuration register (see section 3.23). 14 ? 11 pme_support r pci_pme support. this 4-bit field indicates the power states from which the TSB43AB21A device may assert pci_pme . this field returns a value of 1111b by default, indicating that pci_pme may be asserted from the d3 hot , d2, d1, and d0 power states. 10 d2_support r d2 support. bit 10 is hardwired to 1, indicating that the TSB43AB21A device supports the d2 power state. 9 d1_support r d1 support. bit 9 is hardwired to 1, indicating that the TSB43AB21A device supports the d1 power state. 8 ? 6 aux_current r auxiliary current. this 3-bit field reports the 3.3-v aux auxiliary current requirements. when bit 15 (pme_d3cold) is cleared, this field returns 000b; otherwise, it returns 001b. 000b = self-powered 001b = 55 ma (3.3-v aux maximum current required) 5 dsi r device-specific initialization. this bit returns 0 when read, indicating that the TSB43AB21A device does not require special initialization beyond the standard pci configuration header before a generic class driver is able to use it. 4 rsvd r reserved. bit 4 returns 0 when read. 3 pme_clk r pci_pme clock. this bit returns 0 when read, indicating that no host bus clock is required for the TSB43AB21A device to generate pci_pme . 2 ? 0 pm_version r power-management version. this field returns 010b when read, indicating that the TSB43AB21A device is compatible with the registers described in the pci bus power management interface specification (revision 1.1).
3 ? 15 3.20 power management control and status register the power management control and status register implements the control and status of the pci power management function. this register is not affected by the internally generated reset caused by the transition from the d3 hot to d0 state. see table 3 ? 18 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management control and status type rwc r r r r r r r/w r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management control and status offset: 48h type: read/clear, read/write, read-only default: 0000h table 3 ? 18. power management control and status register description bit field name type description 15 pme_sts rwc bit 15 is set to 1 when the TSB43AB21A device normally asserts the pci_pme signal independent of the state of bit 8 (pme_enb). this bit is cleared by a writeback of 1, which also clears the pci_pme signal driven by the TSB43AB21A device. writing a 0 to this bit has no effect. 14 ? 13 data_scale r this field returns 0s, because the data register is not implemented. 12 ? 9 data_select r this field returns 0s, because the data register is not implemented. 8 pme_enb r/w when bit 8 is set to 1, pme assertion is enabled. when bit 8 is cleared, pme assertion is disabled. this bit defaults to 0 if the function does not support pme generation from d3 cold . if the function supports pme from d3 cold , this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 7 ? 2 rsvd r reserved. bits 7 ? 2 return 0s when read. 1 ? 0 pwr_state r/w power state. this 2-bit field sets the TSB43AB21A device power state and is encoded as follows: 00 = current power state is d0. 01 = current power state is d1. 10 = current power state is d2. 11 = current power state is d3. 3.21 power management extension registers the power management extension register provides extended power-management features not applicable to the TSB43AB21A device; thus, it is read-only and returns 0 when read. see table 3 ? 19 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management extension type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management extension offset: 4ah type: read-only default: 0000h table 3 ? 19. power management extension registers description bit field name type description 15 ? 0 rsvd r reserved. bits 15 ? 0 return 0s when read.
3 ? 16 3.22 pci phy control register the pci phy control register provides a method for enabling the phy cna output. see table 3 ? 20 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pci phy control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pci phy control type r r r r r r r r r/w r r r r/w r r r default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 register: pci phy control offset: ech type: read/write, read-only default: 0000 0008h table 3 ? 20. pci phy control register bit field name type description 31 ? 8 rsvd r reserved. bits 31 ? 8 return 0s when read. 7 cnaout r/w when bit 7 is set to 1, the phy cna output is routed to terminal 96. when implementing a serial eeprom, this bit can be set by programming bit 7 of offset 16h in the eeprom to 1. 6 ? 4 rsvd r reserved. bits 6 ? 4 return 0s when read. these bits are affected when implementing a serial eeprom; thus, bits 6 ? 4 at eeprom byte offset 16h must be programmed to 0. 3 rsvd r/w reserved. bit 3 defaults to 1 to indicate compliance with ieee std 1394a-2000. if a serial eeprom is implemented, bit 3 at eeprom byte offset 16h must be set to 1. see table 6 ? 2, serial eeprom map . 2 ? 0 rsvd r reserved. bits 2 ? 0 return 0s when read. these bits are affected when implementing a serial eeprom; thus, bits 2 ? 0 at eeprom byte offset 16h must be programmed to 0.
3 ? 17 3.23 miscellaneous configuration register the miscellaneous configuration register provides miscellaneous pci-related configuration. see table 3 ? 21 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name miscellaneous configuration type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name miscellaneous configuration type r/w r r/w r r r/w r r r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: miscellaneous configuration offset: f0h type: read/write, read-only default: 0000 0000h table 3 ? 21. miscellaneous configuration register bit field name type description 31 ? 16 rsvd r reserved. bits 31 ? 16 return 0s when read. 15 pme_d3cold r/w pci_pme support from d3 cold . this bit programs bit 15 (pme_d3cold) in the power management capabilities register at offset 46h in the pci configuration space (see section 3.19, power management capabilities register ). 14 ? 5 rsvd r reserved. bits 14 ? 5 return 0s when read. 4 dis_tgt_abt r/w bit 4 defaults to 0, which provides iohci-lynx ? compatible target abort signaling. when this bit is set to 1, it enables the no-target-abort mode, in which the TSB43AB21A device returns indeterminate data instead of signaling target abort. the TSB43AB21A llc is divided into the pci_clk and sclk domains. if software tries to access registers in the link that are not active because the sclk is disabled, a target abort is issued by the link. on some systems, this can cause a problem resulting in a fatal system error. enabling this bit allows the link to respond to these types of requests by returning ffh. it is recommended that this bit be set to 1. 3 gp2iic r/w when bit 3 is set to 1, the gpio3 and gpio2 signals are internally routed to the scl and sda, respectively. the gpio3 and gpio2 terminals are also placed in the high-impedance state. 2 disable_sclkgate r/w when bit 2 is set to 1, the internal sclk runs identically with the chip input. this is a test feature only and must be cleared to 0 (all applications). 1 disable_pcigate r/w when bit 1 is set to 1, the internal pci clock runs identically with the chip input. this is a test feature only and must be cleared to 0 (all applications). 0 keep_pclk r/w when bit 0 is set to 1, the pci clock is always kept running through the pci_clkrun protocol. when this bit is cleared, the pci clock can be stopped using pci_clkrun .
3 ? 18 3.24 link enhancement control register the link enhancement control register implements ti proprietary bits that are initialized by software or by a serial eeprom, if present. after these bits are set to 1, their functionality is enabled only if bit 22 (aphyenhanceenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. see table 3 ? 22 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name link enhancement control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name link enhancement control type r/w r r/w r/w r r/w r r/w r/w r r r r r r/w r default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 register: link enhancement control offset: f4h type: read/write, read-only default: 0000 1000h table 3 ? 22. link enhancement control register description bit field name type description 31 ? 16 rsvd r reserved. bits 31 ? 16 return 0s when read. 15 dis_at_pipeline r/w disable at pipelining. when bit 15 is set to 1, out-of-order at pipelining is disabled. 14 rsvd r reserved. 13 ? 12 atx_thresh r/w this field sets the initial at threshold value, which is used until the at fifo is underrun. when the TSB43AB21A device retries the packet, it uses a 2k-byte threshold, resulting in a store-and-forward operation. 00 = threshold ~ 2k bytes resulting in a store-and-forward operation 01 = threshold ~ 1.7k bytes (default) 10 = threshold ~ 1k bytes 11 = threshold ~ 512 bytes these bits fine-tune the asynchronous transmit threshold. for most applications the 1.7k-byte threshold is optimal. changing this value may increase or decrease the 1394 latency depending on the average pci bus latency. setting the at threshold to 1.7k, 1k, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the fifo. if the packet to be transmitted is larger than the at threshold, the remaining data must be received before the at fifo is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. as a result, the link then commences store-and-forward operation. wait until it has the complete packet in the fifo before retransmitting it on the second attempt to ensure delivery. an at threshold of 2k results in store-and-forward operation, which means that asynchronous data is not transmitted until an end-of-packet token is received. restated, setting the at threshold to 2k results in only complete packets being transmitted. note that this device always uses store-and-forward when the asynchronous transmit retries register at ohci offset 08h (see section 4.3, asynchronous transmit retries register ) is cleared. 11 rsvd r reserved. bit 11 returns 0 when read. 10 enab_mpeg_ts r/w enable mpeg cip timestamp enhancement. when bit 9 is set to 1, the enhancement is enabled for mpeg cip transmit streams (fmt = 20h). 9 rsvd r reserved. bit 9 returns 0 when read. 8 enab_dv_ts r/w enable dv cip timestamp enhancement. when bit 8 is set to 1, the enhancement is enabled for dv cip transmit streams (fmt = 00h). 7 enab_unfair r/w enable asynchronous priority requests. iohci-lynx ? compatible. setting bit 7 to 1 enables the link to respond to requests with priority arbitration. it is recommended that this bit be set to 1.
3 ? 19 table 3 ? 22. link enhancement control register description (continued) bit field name type description 6 rsvd r this bit is not assigned in the TSB43AB21A follow-on products, because this bit location loaded by the serial eeprom from the enhancements field corresponds to bit 23 (programphyenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ). 5 ? 2 rsvd r reserved. bits 5 ? 2 return 0s when read. 1 enab_accel r/w enable acceleration enhancements. iohci-lynx ? compatible. when bit 1 is set to 1, the phy layer is notified that the link supports the ieee std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. it is recommended that this bit be set to 1. 0 rsvd r reserved. bit 0 returns 0 when read. 3.25 subsystem access register write access to the subsystem access register updates the subsystem identification registers identically to iohci-lynx ? . the system id value written to this register may also be read back from this register. see table 3 ? 23 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name subsystem access type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem access type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem access offset: f8h type: read/write default: 0000 0000h table 3 ? 23. subsystem access register description bit field name type description 31 ? 16 subdev_id r/w subsystem device id alias. this field indicates the subsystem device id. 15 ? 0 subven_id r/w subsystem vendor id alias. this field indicates the subsystem vendor id.
3 ? 20 3.26 gpio control register the gpio control register has the control and status bits for the gpio2 and gpio3 ports. see table 3 ? 24 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name gpio control type r/w r r/w r/w r r r rwu r/w r r/w r/w r r r rwu default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name gpio control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: gpio control offset: fch type: read/write/update, read/write, read-only default: 0000 0000h table 3 ? 24. general-purpose input/output control register description bit field name type description 31 int_3en r/w when bit 31 is set to 1, a TSB43AB21A general-purpose interrupt event occurs on a level change of the gpio3 input. this event can generate an interrupt, with mask and event status reported through the interrupt mask register at ohci offset 88h/8ch (see section 4.22, interrupt mask register ) and interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ). 30 rsvd r reserved. bit 30 returns 0 when read. 29 gpio_inv3 r/w gpio3 polarity invert. when bit 29 is set to 1, the polarity of gpio3 is inverted. 28 gpio_enb3 r/w gpio3 enable control. when bit 28 is set to 1, the output is enabled. otherwise, the output is high impedance. 27 ? 25 rsvd r reserved. bits 27 ? 25 return 0s when read. 24 gpio_data3 rwu gpio3 data. reads from bit 24 return the logical value of the input to gpio3. writes to this bit update the value to drive to gpio3 when output is enabled. 23 int_2en r/w when bit 23 is set to 1, a TSB43AB21A general-purpose interrupt event occurs on a level change of the gpio2 input. this event can generate an interrupt, with mask and event status reported through the interrupt mask register at ohci offset 88h/8ch (see section 4.22, interrupt mask register ) and interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ). 22 rsvd r reserved. bit 22 returns 0 when read. 21 gpio_inv2 r/w gpio2 polarity invert. when bit 21 is set to 1, the polarity of gpio2 is inverted. 20 gpio_enb2 r/w gpio2 enable control. when bit 20 is set to 1, the output is enabled. otherwise, the output is high impedance. 19 ? 17 rsvd r reserved. bits 19 ? 17 return 0s when read. 16 gpio_data2 rwu gpio2 data. reads from bit 16 return the logical value of the input to gpio2. writes to this bit update the value to drive to gpio2 when the output is enabled. 15 ? 0 rsvd r reserved. bits 15 ? 0 return 0s when read.
4 ? 1 4 ohci registers the ohci registers defined by the 1394 open host controller interface specification are memory-mapped into a 2k-byte region of memory pointed to by the ohci base address register at offset 10h in pci configuration space (see section 3.9, ohci base address register ). these registers are the primary interface for controlling the TSB43AB21A ieee 1394 link function. this section provides the register interface and bit descriptions. several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. there are two addresses for a set/clear register: registerset and registerclear. see table 4 ? 1 for a register listing. a 1 bit written to registerset causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. a 1 bit written to registerclear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected. typically, a read from either registerset or registerclear returns the contents of the set or clear register, respectively. however, sometimes reading the registerclear provides a masked version of the set or clear register. the interrupt event register is an example of this behavior. table 4 ? 1. ohci register map dma context register name abbreviation offset ? ohci version version 00h guid rom guid_rom 04h asynchronous transmit retries atretries 08h csr data csrdata 0ch csr compare csrcomparedata 10h csr control csrcontrol 14h configuration rom header configromhdr 18h bus identification busid 1ch bus options busoptions 20h guid high guidhi 24h guid low guidlo 28h reserved ? 2ch ? 30h configuration rom mapping configrommap 34h posted write address low postedwriteaddresslo 38h posted write address high postedwriteaddresshi 3ch vendor id vendorid 40h reserved ? 44h ? 4ch host controller control hccontrolset 50h host controller control hccontrolclr 54h reserved ? 58h ? 5ch
4 ? 2 table 4 ? 1. ohci register map (continued) dma context register name abbreviation offset self-id reserved ? 60h self-id buffer pointer selfidbuffer 64h self-id count selfidcount 68h reserved ? 6ch ? isochronous receive channel mask high irchannelmaskhiset 70h isochronous receive channel mask high irchannelmaskhiclear 74h isochronous receive channel mask low irchannelmaskloset 78h isochronous receive channel mask low irchannelmaskloclear 7ch interrupt event inteventset 80h interrupt event inteventclear 84h interrupt mask intmaskset 88h interrupt mask intmaskclear 8ch isochronous transmit interrupt event isoxmitinteventset 90h isochronous transmit interrupt event isoxmitinteventclear 94h isochronous transmit interrupt mask isoxmitintmaskset 98h isochronous transmit interrupt mask isoxmitintmaskclear 9ch ? isochronous receive interrupt event isorecvinteventset a0h isochronous receive interrupt event isorecvinteventclear a4h isochronous receive interrupt mask isorecvintmaskset a8h isochronous receive interrupt mask isorecvintmaskclear ach initial bandwidth available initialbandwidthavailable b0h initial channels available high initialchannelsavailablehi b4h initial channels available low initialchannelsavailablelo b8h reserved ? bch ? d8h fairness control fairnesscontrol dch link control linkcontrolset e0h link control linkcontrolclear e4h node identification nodeid e8h phy layer control phycontrol ech isochronous cycle timer isocyctimer f0h reserved ? f4h ? fch asynchronous request filter high asyncrequestfilterhiset 100h asynchronous request filter high asyncrequestfilterhiclear 104h asynchronous request filter low asyncrequestfilterloset 108h asynchronous request filter low asyncrequestfilterloclear 10ch physical request filter high physicalrequestfilterhiset 110h physical request filter high physicalrequestfilterhiclear 114h physical request filter low physicalrequestfilterloset 118h physical request filter low physicalrequestfilterloclear 11ch physical upper bound physicalupperbound 120h reserved ? 124h ? 17ch
4 ? 3 table 4 ? 1. ohci register map (continued) dma context register name abbreviation offset asynchronous context control contextcontrolset 180h asynchronous asynchronous context control contextcontrolclear 184h asynchronous request transmit reserved ? 188h request transmit [ atrq ] asynchronous context command pointer commandptr 18ch [q] reserved ? 190h ? 19ch asynchronous context control contextcontrolset 1a0h asynchronous asynchronous context control contextcontrolclear 1a4h asynchronous response transmit reserved ? 1a8h res onse transmit [ atrs ] asynchronous context command pointer commandptr 1ach [] reserved ? 1b0h ? 1bch asynchronous context control contextcontrolset 1c0h asynchronous asynchronous context control contextcontrolclear 1c4h asynchronous request receive reserved ? 1c8h request receive [ arrq ] asynchronous context command pointer commandptr 1cch [q] reserved ? 1d0h ? 1dch asynchronous context control contextcontrolset 1e0h asynchronous asynchronous context control contextcontrolclear 1e4h asynchronous response receive reserved ? 1e8h res onse receive [ arrs ] asynchronous context command pointer commandptr 1ech [] reserved ? 1f0h ? 1fch isochronous transmit context control contextcontrolset 200h + 16 x n isochronous isochronous transmit context control contextcontrolclear 204h + 16 x n isochronous transmit context n reserved ? 208h + 16 x n transmit context n n = 0, 1, 2, 3, , 7 isochronous transmit context command pointer commandptr 20ch + 16 x n reserved ? 210h ? 3fch isochronous receive context control contextcontrolset 400h + 32 x n isochronous isochronous receive context control contextcontrolclear 404h + 32 x n i soc h ronous receive context n reserved ? 408h + 32 x n r ece i ve c on t ex t n n = 0, 1, 2, 3 isochronous receive context command pointer commandptr 40ch + 32 x n isochronous receive context match contextmatch 410h + 32 x n
4 ? 4 4.1 ohci version register the ohci version register indicates the ohci version support and whether or not the serial eeprom is present. see table 4 ? 2 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name ohci version type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name ohci version type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 register: ohci version offset: 00h type: read-only default: 0x01 0010h table 4 ? 2. ohci version register description bit field name type description 31 ? 25 rsvd r reserved. bits 31 ? 25 return 0s when read. 24 guid_rom r the TSB43AB21A device sets bit 24 to 1 if the serial eeprom is detected. if the serial eeprom is present, the bus_info_block is automatically loaded on system (hardware) reset. 23 ? 16 version r major version of the ohci. the TSB43AB21A device is compliant with the 1394 open host controller interface specification (revision 1.1); thus, this field reads 01h. 15 ? 8 rsvd r reserved. bits 15 ? 8 return 0s when read. 7 ? 0 revision r minor version of the ohci. the TSB43AB21A device is compliant with the 1394 open host controller interface specification (revision 1.1); thus, this field reads 10h.
4 ? 5 4.2 guid rom register the guid rom register accesses the serial eeprom, and is only applicable if bit 24 (guid_rom) in the ohci version register at ohci offset 00h (see section 4.1, ohci version register) is set to 1. see table 4 ? 3 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name guid rom type rsu r r r r r rsu r ru ru ru ru ru ru ru ru default 0 0 0 0 0 0 0 0 x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guid rom type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: guid rom offset: 04h type: read/set/update, read/update, read-only default: 00xx 0000h table 4 ? 3. guid rom register description bit field name type description 31 addrreset rsu software sets bit 31 to 1 to reset the guid rom address to 0. when the TSB43AB21A device completes the reset, it clears this bit. the TSB43AB21A device does not automatically fill bits 23 ? 16 (rddata field) with the 0 th byte. 30 ? 26 rsvd r reserved. bits 30 ? 26 return 0s when read. 25 rdstart rsu a read of the currently addressed byte is started when bit 25 is set to 1. this bit is automatically cleared when the TSB43AB21A device completes the read of the currently addressed guid rom byte. 24 rsvd r reserved. bit 24 returns 0 when read. 23 ? 16 rddata ru this field contains the data read from the guid rom. 15 ? 8 rsvd r reserved. bits 15 ? 8 return 0s when read. 7 ? 0 minirom r the minirom field defaults to 0 indicating that no mini-rom is implemented. if bit 5 of eeprom offset 6h is set to 1, this field returns 20h indicating that valid mini-rom data begins at offset 20h of the guid rom.
4 ? 6 4.3 asynchronous transmit retries register the asynchronous transmit retries register indicates the number of times the TSB43AB21A device attempts a retry for asynchronous dma request transmit and for asynchronous physical and dma response transmit. see table 4 ? 4 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name asynchronous transmit retries type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asynchronous transmit retries type r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: asynchronous transmit retries offset: 08h type: read/write, read-only default: 0000 0000h table 4 ? 4. asynchronous transmit retries register description bit field name type description 31 ? 29 secondlimit r the second limit field returns 0s when read, because outbound dual-phase retry is not implemented. 28 ? 16 cyclelimit r the cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented. 15 ? 12 rsvd r reserved. bits 15 ? 12 return 0s when read. 11 ? 8 maxphysrespretries r/w this field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 7 ? 4 maxatrespretries r/w this field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 3 ? 0 maxatreqretries r/w this field tells the asynchronous transmit dma request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. 4.4 csr data register the csr data register accesses the bus management csr registers from the host through compare-swap operations. this register contains the data to be stored in a csr if the compare is successful. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csr data type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csr data type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x register: csr data offset: 0ch type: read-only default: xxxx xxxxh
4 ? 7 4.5 csr compare register the csr compare register accesses the bus management csr registers from the host through compare-swap operations. this register contains the data to be compared with the existing value of the csr resource. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csr compare type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csr compare type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x register: csr compare offset: 10h type: read-only default: xxxx xxxxh 4.6 csr control register the csr control register accesses the bus management csr registers from the host through compare-swap operations. this register controls the compare-swap operation and selects the csr resource. see table 4 ? 5 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name csr control type ru r r r r r r r r r r r r r r r default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name csr control type r r r r r r r r r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x register: csr control offset: 14h type: read/write, read/update, read-only default: 8000 000xh table 4 ? 5. csr control register description bit field name type description 31 csrdone ru bit 31 is set to 1 by the TSB43AB21A device when a compare-swap operation is complete. it is cleared whenever this register is written. 30 ? 2 rsvd r reserved. bits 30 ? 2 return 0s when read. 1 ? 0 csrsel r/w this field selects the csr resource as follows: 00 = bus_manager_id 01 = bandwidth_available 10 = channels_available_hi 11 = channels_available_lo
4 ? 8 4.7 configuration rom header register the configuration rom header register externally maps to the first quadlet of the 1394 configuration rom, offset ffff f000 0400h. see table 4 ? 6 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name configuration rom header type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name configuration rom header type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x x x x x x x x x register: configuration rom header offset: 18h type: read/write default: 0000 xxxxh table 4 ? 6. configuration rom header register description bit field name type description 31 ? 24 info_length r/w ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 23 ? 16 crc_length r/w ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 15 ? 0 rom_crc_value r/w ieee 1394 bus-management field. must be valid at any time bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. the reset value is undefined if no serial eeprom is present. if a serial eeprom is present, this field is loaded from the serial eeprom. 4.8 bus identification register the bus identification register externally maps to the first quadlet in the bus_info_block and contains the constant 3133 3934h, which is the ascii value of 1394. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bus identification type r r r r r r r r r r r r r r r r default 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bus identification type r r r r r r r r r r r r r r r r default 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0 register: bus identification offset: 1ch type: read-only default: 3133 3934h
4 ? 9 4.9 bus options register the bus options register externally maps to the second quadlet of the bus_info_block. see table 4 ? 7 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name bus options type r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w default x x x x 0 0 0 0 x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bus options type r/w r/w r/w r/w r r r r r/w r/w r r r r r r default 1 0 1 0 0 0 0 0 x x 0 0 0 0 1 0 register: bus options offset: 20h type: read/write, read-only default: x0xx a0x2h table 4 ? 7. bus options register description bit field name type description 31 irmc r/w isochronous resource-manager capable. ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 30 cmc r/w cycle master capable. ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 29 isc r/w isochronous support capable. ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 28 bmc r/w bus manager capable. ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 27 pmc r/w power-management capable. ieee 1394 bus-management field. when bit 27 is set to 1, this indicates that the node is power-management capable. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 26 ? 24 rsvd r reserved. bits 26 ? 24 return 0s when read. 23 ? 16 cyc_clk_acc r/w cycle master clock accuracy, in parts per million. ieee 1394 bus-management field. must be valid when bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. 15 ? 12 max_rec r/w maximum request. ieee 1394 bus-management field. hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. this value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). software may change this field; however, this field must be valid at any time bit 17 (linkenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1. a received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. this field is not affected by a software reset, and defaults to value indicating 2048 bytes on a system (hardware) reset. 11 ? 8 rsvd r reserved. bits 11 ? 8 return 0s when read. 7 ? 6 g r/w generation counter. this field is incremented if any portion of the configuration rom has been incremented since the prior bus reset. 5 ? 3 rsvd r reserved. bits 5 ? 3 return 0s when read. 2 ? 0 lnk_spd r link speed. this field returns 010, indicating that the link speeds of 100m bits/s, 200m bits/s, and 400m bits/s are supported.
4 ? 10 4.10 guid high register the guid high register represents the upper quadlet in a 64-bit global unique id (guid) which maps to the third quadlet in the bus_info_block. this register contains node_vendor_id and chip_id_hi fields. this register initializes to 0s on a system (hardware) reset, which is an illegal guid value. if a serial eeprom is detected, the contents of this register are loaded through the serial eeprom interface after a g_rst . at that point, the contents of this register cannot be changed. if no serial eeprom is detected, the contents of this register are loaded by the bios after a pci_rst . at that point, the contents of this register cannot be changed. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name guid high type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guid high type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: guid high offset: 24h type: read-only default: 0000 0000h 4.11 guid low register the guid low register represents the lower quadlet in a 64-bit global unique id (guid) which maps to chip_id_lo in the bus_info_block. this register initializes to 0s on a system (hardware) reset and behaves identical to the guid high register at ohci offset 24h (see section 4.10, guid high register ). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name guid low type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name guid low type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: guid low offset: 28h type: read-only default: 0000 0000h
4 ? 11 4.12 configuration rom mapping register the configuration rom mapping register contains the start address within system memory that maps to the start address of 1394 configuration rom for this node. see table 4 ? 8 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name configuration rom mapping type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name configuration rom mapping type r/w r/w r/w r/w r/w r/w r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: configuration rom mapping offset: 34h type: read/write default: 0000 0000h table 4 ? 8. configuration rom mapping register description bit field name type description 31 ? 10 configromaddr r/w if a quadlet read request to 1394 offset ffff f000 0400h through offset ffff f000 07ffh is received, the low-order 10 bits of the offset are added to this register to determine the host memory address of the read request. 9 ? 0 rsvd r reserved. bits 9 ? 0 return 0s when read. 4.13 posted write address low register the posted write address low register communicates error information if a write request is posted and an error occurs while the posted data packet is being written. see table 4 ? 9 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name posted write address low type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name posted write address low type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default x x x x x x x x x x x x x x x x register: posted write address low offset: 38h type: read/update default: xxxx xxxxh table 4 ? 9. posted write address low register description bit field name type description 31 ? 0 offsetlo ru the lower 32 bits of the 1394 destination offset of the write request that failed.
4 ? 12 4.14 posted write address high register the posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. see table 4 ? 10 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name posted write address high type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name posted write address high type ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru ru default x x x x x x x x x x x x x x x x register: posted write address high offset: 3ch type: read/update default: xxxx xxxxh table 4 ? 10. posted write address high register description bit field name type description 31 ? 16 sourceid ru this field is the 10-bit bus number (bits 31 ? 22) and 6-bit node number (bits 21 ? 16) of the node that issued the write request that failed. 15 ? 0 offsethi ru the upper 16 bits of the 1394 destination offset of the write request that failed. 4.15 vendor id register the vendor id register holds the company id of an organization that specifies any vendor-unique registers. the TSB43AB21A device implements texas instruments unique behavior with regards to ohci. thus, this register is read-only and returns 0108 0028h when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 register: vendor id offset: 40h type: read-only default: 0108 0028h
4 ? 13 4.16 host controller control register the host controller control set/clear register pair provides flags for controlling the TSB43AB21A device. see table 4 ? 11 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name host controller control type rsu rsc rsc r r r r r r rsc r r rsc rsc rsc rscu default 0 x 0 0 0 0 0 0 1 0 0 0 0 x 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name host controller control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: host controller control offset: 50h set register 54h clear register type: read/set/clear/update, read/set/clear, read/cear, read-only default: x08x 0000h table 4 ? 11. host controller control register description bit field name type description 31 bibimage valid rsu when bit 31 is set to 1, the TSB43AB21A physical response unit is enabled to respond to block read requests to host configuration rom and to the mechanism for atomically updating configuration rom. software creates a valid image of the bus_info_block in host configuration rom before setting this bit. when this bit is cleared, the TSB43AB21A device returns ack_type_error on block read requests to host configuration rom. also, when this bit is cleared and a 1394 bus reset occurs, the configuration rom mapping register at ohci offset 34h (see section 4.12, configuration rom mapping register ), configuration rom header register at ohci offset 18h (see section 4.7, configuration rom header register ), and bus options register at ohci offset 20h (see section 4.9, bus options register ) are not updated. software can set this bit only when bit 17 (linkenable) is 0. once bit 31 is set to 1, it can be cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the TSB43AB21A device loads bus_info_block registers from host memory. 30 nobyteswapdata rsc bit 30 controls whether physical accesses to locations outside the TSB43AB21A device itself, as well as any other dma data accesses are byte swapped. 29 acktardyenable rsc bit 29 controls the acknowledgement of ack_tardy. when bit 29 is set to 1, ack_tardy may be returned as an acknowledgment to accesses from the 1394 bus to the TSB43AB21A device, including accesses to the bus_info_block. the TSB43AB21A device returns ack_tardy to all other asynchronous packets addressed to the TSB43AB21A node. when the TSB43AB21A device sends ack_tardy, bit 27 (ack_tardy) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) is set to 1 to indicate the attempted asynchronous access. software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. software also unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register before placing the TSB43AB21A device into the d1 power mode. software must not set this bit if the TSB43AB21A node is the 1394 bus manager. 28 ? 24 rsvd r reserved. bits 28 ? 24 return 0s when read. 23 programphyenable r bit 23 informs upper-level software that lower-level software has consistently configured the ieee 1394a-2000 enhancements in the link and phy layers. when this bit is 1, generic software such as the ohci driver is responsible for configuring ieee 1394a-2000 enhancements in the phy layer and bit 22 (aphyenhanceenable). when this bit is 0, the generic software may not modify the ieee 1394a-2000 enhancements in the phy layer and cannot interpret the setting of bit 22 (aphyenhanceenable). this bit is initialized from serial eeprom. this bit defaults to 1.
4 ? 14 table 4 ? 11. host controller control register description (continued) bit field name type description 22 aphyenhanceenable rsc when bits 23 (programphyenable) and 17 (linkenable) are 1, the ohci driver can set bit 22 to 1 to use all ieee 1394a-2000 enhancements. when bit 23 (programphyenable) is cleared to 0, the software does not change phy enhancements or this bit. 21 ? 20 rsvd r reserved. bits 21 and 20 return 0s when read. 19 lps rsc bit 19 controls the link power status. software must set this bit to 1 to permit the link-phy communication. a 0 prevents link-phy communication. the ohci-link is divided into two clock domains (pci_clk and phy_sclk). if software tries to access any register in the phy_sclk domain while the phy_sclk is disabled, a target abort is issued by the link. this problem can be avoided by setting bit 4 (dis_tgt_abt) to 1 in the miscellaneous configuration register at offset f0h in the pci configuration space (see section 3.23, miscellaneous configuration register ). this allows the link to respond to these types of request by returning all fs (hex). ohci registers at offsets dch ? f0h and 100h ? 11ch are in the phy_sclk domain. after setting lps, software must wait approximately 10 ms before attempting to access any of the ohci registers. this gives the phy_sclk time to stabilize. 18 postedwriteenable rsc bit 18 enables (1) or disables (0) posted writes. software changes this bit only when bit 17 (linkenable) is 0. 17 linkenable rsc bit 17 is cleared to 0 by either a system (hardware) or software reset. software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. this bit is necessary to keep other nodes from sending transactions before the local system is ready. when this bit is cleared, the TSB43AB21A device is logically and immediately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. 16 softreset rscu when bit 16 is set to 1, all TSB43AB21A states are reset, all fifos are flushed, and all ohci registers are set to their system (hardware) reset values, unless otherwise specified. pci registers are not affected by this bit. this bit remains set to 1 while the software reset is in progress and reverts back to 0 when the reset has completed. 15 ? 0 rsvd r reserved. bits 15 ? 0 return 0s when read. 4.17 self-id buffer pointer register the self-id buffer pointer register points to the 2k-byte aligned base address of the buffer in host memory where the self-id packets are stored during bus initialization. bits 31 ? 11 are read/write accessible. bits 10 ? 0 are reserved, and return 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name self-id buffer pointer type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name self-id buffer pointer type r/w r/w r/w r/w r/w r r r r r r r r r r r default x x x x x 0 0 0 0 0 0 0 0 0 0 0 register: self-id buffer pointer offset: 64h type: read/write, read-only default: xxxx xx00h
4 ? 15 4.18 self-id count register the self-id count register keeps a count of the number of times the bus self-id process has occurred, flags self-id packet errors, and keeps a count of the self-id data in the self-id buffer. see table 4 ? 12 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name self-id count type ru r r r r r r r ru ru ru ru ru ru ru ru default x 0 0 0 0 0 0 0 x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name self-id count type r r r r r ru ru ru ru ru ru ru ru ru r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: self-id count offset: 68h type: read/update, read-only default: x0xx 0000h table 4 ? 12. self-id count register description bit field name type description 31 selfiderror ru when bit 31 is set to 1, an error was detected during the most recent self-id packet reception. the contents of the self-id buffer are undefined. this bit is cleared after a self-id reception in which no errors are detected. note that an error can be a hardware error or a host bus write error. 30 ? 24 rsvd r reserved. bits 30 ? 24 return 0s when read. 23 ? 16 selfidgeneration ru the value in this field increments each time a bus reset is detected. this field rolls over to 0 after reaching 255. 15 ? 11 rsvd r reserved. bits 15 ? 11 return 0s when read. 10 ? 2 selfidsize ru this field indicates the number of quadlets that have been written into the self-id buffer for the current bits 23 ? 16 (selfidgeneration field). this includes the header quadlet and the self-id data. this field is cleared to 0s when the self-id reception begins. 1 ? 0 rsvd r reserved. bits 1 and 0 return 0s when read.
4 ? 16 4.19 isochronous receive channel mask high register the isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. a read from either the set register or clear register returns the content of the isochronous receive channel mask high register. see table 4 ? 13 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive channel mask high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive channel mask high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x x x x x x x x x x x x x x x register: isochronous receive channel mask high offset: 70h set register 74h clear register type: read/set/clear default: xxxx xxxxh table 4 ? 13. isochronous receive channel mask high register description bit field name type description 31 isochannel63 rsc when bit 31 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 63. 30 isochannel62 rsc when bit 30 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 62. 29 isochannel61 rsc when bit 29 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 61. 28 isochannel60 rsc when bit 28 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 60. 27 isochannel59 rsc when bit 27 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 59. 26 isochannel58 rsc when bit 26 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 58. 25 isochannel57 rsc when bit 25 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 57. 24 isochannel56 rsc when bit 24 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 56. 23 isochannel55 rsc when bit 23 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 55. 22 isochannel54 rsc when bit 22 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 54. 21 isochannel53 rsc when bit 21 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 53. 20 isochannel52 rsc when bit 20 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 52. 19 isochannel51 rsc when bit 19 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 51. 18 isochannel50 rsc when bit 18 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 50. 17 isochannel49 rsc when bit 17 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 49. 16 isochannel48 rsc when bit 16 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 48. 15 isochannel47 rsc when bit 15 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 47. 14 isochannel46 rsc when bit 14 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 46. 13 isochannel45 rsc when bit 13 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 45. 12 isochannel44 rsc when bit 12 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 44. 11 isochannel43 rsc when bit 11 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 43. 10 isochannel42 rsc when bit 10 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 42. 9 isochannel41 rsc when bit 9 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 41. 8 isochannel40 rsc when bit 8 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 40. 7 isochannel39 rsc when bit 7 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 39.
4 ? 17 table 4 ? 13. isochronous receive channel mask high register description (continued) bit field name type description 6 isochannel38 rsc when bit 6 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 38. 5 isochannel37 rsc when bit 5 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 37. 4 isochannel36 rsc when bit 4 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 36. 3 isochannel35 rsc when bit 3 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 35. 2 isochannel34 rsc when bit 2 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 34. 1 isochannel33 rsc when bit 1 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 33. 0 isochannel32 rsc when bit 0 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 32. 4.20 isochronous receive channel mask low register the isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. see table 4 ? 14 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive channel mask low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive channel mask low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x x x x x x x x x x x x x x x register: isochronous receive channel mask low offset: 78h set register 7ch clear register type: read/set/clear default: xxxx xxxxh table 4 ? 14. isochronous receive channel mask low register description bit field name type description 31 isochannel31 rsc when bit 31 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 31. 30 isochannel30 rsc when bit 30 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 30. 29 ? 2 isochanneln rsc bits 29 through 2 (isochanneln, where n = 29, 28, 27, , 2) follow the same pattern as bits 31 and 30. 1 isochannel1 rsc when bit 1 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 1. 0 isochannel0 rsc when bit 0 is set to 1, the TSB43AB21A device is enabled to receive from isochronous channel number 0.
4 ? 18 4.21 interrupt event register the interrupt event set/clear register reflects the state of the various TSB43AB21A interrupt sources. the interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. this register is fully compliant with the 1394 open host controller interface specification , and the TSB43AB21A device adds a vendor-specific interrupt function to bit 30. when the interrupt event register is read, the return value is the bit-wise and function of the interrupt event and interrupt mask registers. see table 4 ? 15 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name interrupt event type r rsc rsc r rscu rscu rscu rscu rscu rscu rscu rscu rscu rscu rscu rscu default 0 x 0 0 0 x x x x x x x x 0 x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name interrupt event type rscu r r r r r rscu rscu ru ru rscu rscu rscu rscu rscu rscu default 0 0 0 0 0 0 x x x x x x x x x x register: interrupt event offset: 80h set register 84h clear register [returns the content of the interrupt event register bit-wise anded with the interrupt mask register when read] type: read/set/clear/update, read/set/clear, read/update, read-only default: xxxx 0xxxh table 4 ? 15. interrupt event register description bit field name type description 31 rsvd r reserved. bit 31 returns 0 when read. 30 vendorspecific rsc this vendor-specific interrupt event is reported when either of the general-purpose interrupts are asserted. the general-purpose interrupts are enabled by setting the corresponding bits int_3en and int_2en (bits 31 and 23, respectively) to 1 in the gpio control register at offset fch in the pci configuration space (see section 3.26, gpio control register ). 29 softinterrupt rsc bit 29 is used by software to generate a TSB43AB21A interrupt for its own use. 28 rsvd r reserved. bit 28 returns 0 when read. 27 ack_tardy rscu bit 27 is set to 1 when bit 29 (acktardyenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ) is set to 1 and any of the following conditions occur: a. data is present in a receive fifo that is to be delivered to the host. b. the physical response unit is busy processing requests or sending responses. c. the TSB43AB21A device sent an ack_tardy acknowledgment. 26 phyregrcvd rscu the TSB43AB21A device has received a phy register data byte which can be read from bits 23 ? 16 in the phy layer control register at ohci offset ech (see section 4.33, phy layer control register ). 25 cycletoolong rscu if bit 21 (cyclemaster) in the link control register at ohci offset e0h/e4h (see section 4.31, link control register ) is set to 1, this indicates that over 125 s has elapsed between the start of sending a cycle start packet and the end of a subaction gap. bit 21 (cyclemaster) in the link control register is cleared by this event. 24 unrecoverableerror rscu this event occurs when the TSB43AB21A device encounters any error that forces it to stop operations on any or all of its subunits, for example, when a dma context sets its dead bit to 1. while bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1.
4 ? 19 table 4 ? 15. interrupt event register description (continued) bit field name type description 23 cycleinconsistent rscu a cycle start was received that had values for the cycleseconds and cyclecount fields that are different from the values in bits 31 ? 25 (cycleseconds field) and bits 24 ? 12 (cyclecount field) in the isochronous cycle timer register at ohci offset f0h (see section 4.34, isochronous cycle timer register ). 22 cyclelost rscu a lost cycle is indicated when no cycle_start packet is sent or received between two successive cyclesynch events. a lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cyclesynch event or if an arbitration reset gap is detected after a cyclesynch event without an intervening cycle start. bit 22 may be set to 1 either when a lost cycle occurs or when logic predicts that one will occur. 21 cycle64seconds rscu indicates that the 7 th bit of the cycle second counter has changed. 20 cyclesynch rscu indicates that a new isochronous cycle has started. bit 20 is set to 1 when the low-order bit of the cycle count toggles. 19 phy rscu indicates that the phy layer requests an interrupt through a status transfer. 18 regaccessfail rscu indicates that a TSB43AB21A register access has failed due to a missing sclk clock signal from the phy layer. when a register access fails, bit 18 is set to 1 before the next register access. 17 busreset rscu indicates that the phy layer has entered bus reset mode. 16 selfidcomplete rscu a self-id packet stream has been received. it is generated at the end of the bus initialization process. bit 16 is turned off simultaneously when bit 17 (busreset) is turned on. 15 selfidcomplete2 rscu secondary indication of the end of a self-id packet stream. bit 15 is set to 1 by the TSB43AB21A device when it sets bit 16 (selfidcomplete), and retains the state, independent of bit 17 (busreset). 14 ? 10 rsvd r reserved. bits 14 ? 10 return 0s when read. 9 lockresperr rscu indicates that the TSB43AB21A device sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. 8 postedwriteerr rscu indicates that a host bus error occurred while the TSB43AB21A device was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. 7 isochrx ru isochronous receive dma interrupt. indicates that one or more isochronous receive contexts have generated an interrupt. this is not a latched event; it is the logical or of all bits in the isochronous receive interrupt event register at ohci offset a0h/a4h (see section 4.25, isochronous receive interrupt event register ) and isochronous receive interrupt mask register at ohci offset a8h/ach (see section 4.26, isochronous receive interrupt mask register ). the isochronous receive interrupt event register indicates which contexts have been interrupted. 6 isochtx ru isochronous transmit dma interrupt. indicates that one or more isochronous transmit contexts have generated an interrupt. this is not a latched event; it is the logical or of all bits in the isochronous transmit interrupt event register at ohci offset 90h/94h (see section 4.23, isochronous transmit interrupt event register ) and isochronous transmit interrupt mask register at ohci offset 98h/9ch (see section 4.24, isochronous transmit interrupt mask register ). the isochronous transmit interrupt event register indicates which contexts have been interrupted. 5 rspkt rscu indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferstatus and rescount fields have been updated. 4 rqpkt rscu indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferstatus and rescount fields have been updated. 3 arrs rscu asynchronous receive response dma interrupt. bit 3 is conditionally set to 1 upon completion of an arrs dma context command descriptor. 2 arrq rscu asynchronous receive request dma interrupt. bit 2 is conditionally set to 1 upon completion of an arrq dma context command descriptor. 1 resptxcomplete rscu asynchronous response transmit dma interrupt. bit 1 is conditionally set to 1 upon completion of an atrs dma command. 0 reqtxcomplete rscu asynchronous request transmit dma interrupt. bit 0 is conditionally set to 1 upon completion of an atrq dma command.
4 ? 20 4.22 interrupt mask register the interrupt mask set/clear register enables the various TSB43AB21A interrupt sources. reads from either the set register or the clear register always return the contents of the interrupt mask register. in all cases except masterintenable (bit 31) and vendorspecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in table 4 ? 15. this register is fully compliant with the 1394 open host controller interface specification and the TSB43AB21A device adds an interrupt function to bit 30. see table 4 ? 16 for a complete description of bits 31 and 30. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name interrupt mask type rscu rsc rsc r rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x 0 0 0 x x x x x x x x 0 x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name interrupt mask type rsc r r r r r rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 x x x x x x x x x x register: interrupt mask offset: 88h set register 8ch clear register type: read/set/clear/update, read/set/clear, read/update, read-only default: xxxx 0xxxh table 4 ? 16. interrupt mask register description bit field name type description 31 masterintenable rscu master interrupt enable. if bit 31 is set to 1, external interrupts are generated in accordance with the interrupt mask register. if this bit is cleared, external interrupts are not generated regardless of the interrupt mask register settings. 30 vendorspecific rsc when this bit and bit 30 (vendorspecific) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this vendor-specific interrupt mask enables interrupt generation. 29 softinterrupt rsc when this bit and bit 29 (softinterrupt) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this soft-interrupt mask enables interrupt generation. 28 rsvd r reserved. bit 28 returns 0 when read. 27 ack_tardy rsc when this bit and bit 27 (ack_tardy) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this acknowledge-tardy interrupt mask enables interrupt generation. 26 phyregrcvd rsc when this bit and bit 26 (phyregrcvd) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this phy-register interrupt mask enables interrupt generation. 25 cycletoolong rsc when this bit and bit 25 (cycletoolong) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this cycle-too-long interrupt mask enables interrupt generation. 24 unrecoverableerror rsc when this bit and bit 24 (unrecoverableerror) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this unrecoverable-error interrupt mask enables interrupt generation. 23 cycleinconsistent rsc when this bit and bit 23 (cycleinconsistent) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this inconsistent-cycle interrupt mask enables interrupt generation. 22 cyclelost rsc when this bit and bit 22 (cyclelost) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this lost-cycle interrupt mask enables interrupt generation.
4 ? 21 table 4 ? 16. interrupt mask register description (continued) bit field name type description 21 cycle64seconds rsc when this bit and bit 21 (cycle64seconds) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this 64-second-cycle interrupt mask enables interrupt generation. 20 cyclesynch rsc when this bit and bit 20 (cyclesynch) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this isochronous-cycle interrupt mask enables interrupt generation. 19 phy rsc when this bit and bit 19 (phy) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this phy-status-transfer interrupt mask enables interrupt generation. 18 regaccessfail rsc when this bit and bit 18 (regaccessfail) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this register-access-failed interrupt mask enables interrupt generation. 17 busreset rsc when this bit and bit 17 (busreset) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this bus-reset interrupt mask enables interrupt generation. 16 selfidcomplete rsc when this bit and bit 16 (selfidcomplete) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this self-id-complete interrupt mask enables interrupt generation. 15 selfidcomplete2 rsc when this bit and bit 15 (selfidcomplete2) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this second-self-id-complete interrupt mask enables interrupt generation. 14 ? 10 rsvd r reserved. bits 14 ? 10 return 0s when read. 9 lockresperr rsc when this bit and bit 9 (lockresperr) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this lock-response-error interrupt mask enables interrupt generation. 8 postedwriteerr rsc when this bit and bit 8 (postedwriteerr) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this posted-write-error interrupt mask enables interrupt generation. 7 isochrx rsc when this bit and bit 7 (isochrx) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this isochronous-receive-dma interrupt mask enables interrupt generation. 6 isochtx rsc when this bit and bit 6 (isochtx) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this isochronous-transmit-dma interrupt mask enables interrupt generation. 5 rspkt rsc when this bit and bit 5 (rspkt) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this receive-response-packet interrupt mask enables interrupt generation. 4 rqpkt rsc when this bit and bit 4 (rqpkt) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this receive-request-packet interrupt mask enables interrupt generation. 3 arrs rsc when this bit and bit 3 (arrs) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this asynchronous-receive-response-dma interrupt mask enables interrupt generation. 2 arrq rsc when this bit and bit 2 (arrq) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this asynchronous-receive-request-dma interrupt mask enables interrupt generation. 1 resptxcomplete rsc when this bit and bit 1 (resptxcomplete) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this response-transmit-complete interrupt mask enables interrupt generation. 0 reqtxcomplete rsc when this bit and bit 0 (reqtxcomplete) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) are set to 1, this request-transmit-complete interrupt mask enables interrupt generation.
4 ? 22 4.23 isochronous transmit interrupt event register the isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. an interrupt is generated on behalf of an isochronous transmit context if an output_last* command completes and its interrupt bits are set to 1. upon determining that the isochtx (bit 6) interrupt has occurred in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ), software can check this register to determine which context(s) caused the interrupt. the interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. see table 4 ? 17 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous transmit interrupt event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous transmit interrupt event type r r r r r r r r rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 x x x x x x x x register: isochronous transmit interrupt event offset: 90h set register 94h clear register [returns the contents of the isochronous transmit interrupt event register bit-wise anded with the isochronous transmit interrupt mask register when read] type: read/set/clear, read-only default: 0000 00xxh table 4 ? 17. isochronous transmit interrupt event register description bit field name type description 31 ? 8 rsvd r reserved. bits 31 ? 8 return 0s when read. 7 isoxmit7 rsc isochronous transmit channel 7 caused the interrupt event register bit 6 (isochtx) interrupt. 6 isoxmit6 rsc isochronous transmit channel 6 caused the interrupt event register bit 6 (isochtx) interrupt. 5 isoxmit5 rsc isochronous transmit channel 5 caused the interrupt event register bit 6 (isochtx) interrupt. 4 isoxmit4 rsc isochronous transmit channel 4 caused the interrupt event register bit 6 (isochtx) interrupt. 3 isoxmit3 rsc isochronous transmit channel 3 caused the interrupt event register bit 6 (isochtx) interrupt. 2 isoxmit2 rsc isochronous transmit channel 2 caused the interrupt event register bit 6 (isochtx) interrupt. 1 isoxmit1 rsc isochronous transmit channel 1 caused the interrupt event register bit 6 (isochtx) interrupt. 0 isoxmit0 rsc isochronous transmit channel 0 caused the interrupt event register bit 6 (isochtx) interrupt.
4 ? 23 4.24 isochronous transmit interrupt mask register the isochronous transmit interrupt mask set/clear register enables the isochtx interrupt source on a per-channel basis. reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. in all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in table 4 ? 17. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous transmit interrupt mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous transmit interrupt mask type r r r r r r r r rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 x x x x x x x x register: isochronous transmit interrupt mask offset: 98h set register 9ch clear register type: read/set/clear, read-only default: 0000 00xxh 4.25 isochronous receive interrupt event register the isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. an interrupt is generated on behalf of an isochronous receive context if an input_* command completes and its interrupt bits are set to 1. upon determining that the isochrx (bit 7) interrupt in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) has occurred, software can check this register to determine which context(s) caused the interrupt. the interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. the only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. see table 4 ? 18 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive interrupt event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive interrupt event type r r r r r r r r r r r r rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 x x x x register: isochronous receive interrupt event offset: a0h set register a4h clear register [returns the contents of isochronous receive interrupt event register bit-wise anded with the isochronous receive mask register when read] type: read/set/clear, read-only default: 0000 000xh table 4 ? 18. isochronous receive interrupt event register description bit field name type description 31 ? 4 rsvd r reserved. bits 31 ? 4 return 0s when read. 3 isorecv3 rsc isochronous receive channel 3 caused the interrupt event register bit 7 (isochrx) interrupt. 2 isorecv2 rsc isochronous receive channel 2 caused the interrupt event register bit 7 (isochrx) interrupt. 1 isorecv1 rsc isochronous receive channel 1 caused the interrupt event register bit 7 (isochrx) interrupt. 0 isorecv0 rsc isochronous receive channel 0 caused the interrupt event register bit 7 (isochrx) interrupt.
4 ? 24 4.26 isochronous receive interrupt mask register the isochronous receive interrupt mask set/clear register enables the isochrx interrupt source on a per-channel basis. reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. in all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in table 4 ? 18. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive interrupt mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive interrupt mask type r r r r r r r r r r r r rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 x x x x register: isochronous receive interrupt mask offset: a8h set register ach clear register type: read/set/clear, read-only default: 0000 000xh 4.27 initial bandwidth available register the initial bandwidth available register value is loaded into the corresponding bus management csr register on a system (hardware) or software reset. see table 4 ? 19 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name initial bandwidth available type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name initial bandwidth available type r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 register: initial bandwidth available offset: b0h type: read-only, read/write default: 0000 1333h table 4 ? 19. initial bandwidth available register description bit field name type description 31 ? 13 rsvd r reserved. bits 31 ? 13 return 0s when read. 12 ? 0 initbwavailable r/w this field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394 bus reset. the value of this field is loaded into the bandwidth_available csr register upon a g_rst , pci_rst , or a 1394 bus reset.
4 ? 25 4.28 initial channels available high register the initial channels available high register value is loaded into the corresponding bus management csr register on a system (hardware) or software reset. see table 4 ? 20 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name initial channels available high type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name initial channels available high type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 register: initial channels available high offset: b4h type: read/write default: ffff ffffh table 4 ? 20. initial channels available high register description bit field name type description 31 ? 0 initchanavailhi r/w this field is reset to ffff_ffffh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. the value of this field is loaded into the channels_available_hi csr register upon a g_rst , pci_rst , or a 1394 bus reset. 4.29 initial channels available low register the initial channels available low register value is loaded into the corresponding bus management csr register on a system (hardware) or software reset. see table 4 ? 21 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name initial channels available low type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name initial channels available low type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 register: initial channels available low offset: b8h type: read/write default: ffff ffffh table 4 ? 21. initial channels available low register description bit field name type description 31 ? 0 initchanavaillo r/w this field is reset to ffff_ffffh on a system (hardware) or software reset, and is not affected by a 1394 bus reset. the value of this field is loaded into the channels_available_lo csr register upon a g_rst , pci_rst , or a 1394 bus reset.
4 ? 26 4.30 fairness control register the fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. see table 4 ? 22 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name fairness control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name fairness control type r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: fairness control offset: dch type: read-only default: 0000 0000h table 4 ? 22. fairness control register description bit field name type description 31 ? 8 rsvd r reserved. bits 31 ? 8 return 0s when read. 7 ? 0 pri_req r/w this field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the phy layer during a fairness interval.
4 ? 27 4.31 link control register the link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB43AB21A device. it contains controls for the receiver and cycle timer. see table 4 ? 23 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name link control type r r r r r r r r r rsc rscu rsc r r r r default 0 0 0 0 0 0 0 0 0 x x x 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name link control type r r r r r rsc rsc r r rs r r r r r r default 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 register: link control offset: e0h set register e4h clear register type: read/set/clear/update, read/set/clear, read-only default: 00x0 0x00h table 4 ? 23. link control register description bit field name type description 31 ? 23 rsvd r reserved. bits 31 ? 23 return 0s when read. 22 cyclesource rsc when bit 22 is set to 1, the cycle timer uses an external source (cyclein) to determine when to roll over the cycle timer. when this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-mhz clock (125 s). 21 cyclemaster rscu when bit 21 is set to 1, the TSB43AB21A device is root and it generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22 (cyclesource). when bit 21 is cleared, the iohci-lynx ? accepts received cycle start packets to maintain synchronization with the node which is sending them. bit 21 is automatically cleared when bit 25 (cycletoolong) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) is set to 1. bit 21 cannot be set to 1 until bit 25 (cycletoolong) is cleared. 20 cycletimerenable rsc when bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-mhz clock and rolls over at the appropriate time, based on the settings of the above bits. when this bit is cleared, the cycle timer offset does not count. 19 ? 11 rsvd r reserved. bits 19 ? 11 return 0s when read. 10 rcvphypkt rsc when bit 10 is set to 1, the receiver accepts incoming phy packets into the ar request context if the ar request context is enabled. this bit does not control receipt of self-identification packets. 9 rcvselfid rsc when bit 9 is set to 1, the receiver accepts incoming self-identification packets. before setting this bit to 1, software must ensure that the self-id buffer pointer register contains a valid address. 8 ? 7 rsvd r reserved. bits 8 and 7 return 0s when read. 6 tag1syncfilterlock rs when bit 6 is set to 1, bit 6 (tag1syncfilter) in the isochronous receive context match register (see section 4.46, isochronous receive context match register ) is set to 1 for all isochronous receive contexts. when bit 6 is cleared, bit 6 (tag1syncfilter) in the isochronous receive context match register has read/write access. this bit is cleared when g_rst is asserted. 5 ? 0 rsvd r reserved. bits 5 ? 0 return 0s when read.
4 ? 28 4.32 node identification register the node identification register contains the address of the node on which the iohci-lynx ? chip resides and indicates the valid node number status. the 16-bit combination of the busnumber field (bits 15 ? 6) and the nodenumber field (bits 5 ? 0) is referred to as the node id. see table 4 ? 24 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name node identification type ru ru r r ru r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name node identification type rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu ru ru ru ru ru ru default 1 1 1 1 1 1 1 1 1 1 x x x x x x register: node identification offset: e8h type: read/write/update, read/update, read-only default: 0000 ffxxh table 4 ? 24. node identification register description bit field name type description 31 idvalid ru bit 31 indicates whether or not the TSB43AB21A device has a valid node number. it is cleared when a 1394 bus reset is detected and set to 1 when the TSB43AB21A device receives a new node number from its phy layer. 30 root ru bit 30 is set to 1 during the bus reset process if the attached phy layer is root. 29 ? 28 rsvd r reserved. bits 29 and 28 return 0s when read. 27 cps ru bit 27 is set to 1 if the phy layer is reporting that cable power status is ok. 26 ? 16 rsvd r reserved. bits 26 ? 16 return 0s when read. 15 ? 6 busnumber rwu this field identifies the specific 1394 bus the TSB43AB21A device belongs to when multiple 1394-compatible buses are connected via a bridge. 5 ? 0 nodenumber ru this field is the physical node number established by the phy layer during self-identification. it is automatically set to the value received from the phy layer after the self-identification phase. if the phy layer sets the nodenumber to 63, software must not set bit 15 (run) in the asynchronous context control register (see section 4.40, asynchronous context control register ) for either of the at dma contexts.
4 ? 29 4.33 phy layer control register the phy layer control register reads from or writes to a phy register. see table 4 ? 25 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name phy layer control type ru r r r ru ru ru ru ru ru ru ru ru ru ru ru default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name phy layer control type rwu rwu r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: phy layer control offset: ech type: read/write/update, read/write, read/update, read-only default: 0000 0000h table 4 ? 25. phy control register description bit field name type description 31 rddone ru bit 31 is cleared to 0 by the TSB43AB21A device when either bit 15 (rdreg) or bit 14 (wrreg) is set to 1. this bit is set to 1 when a register transfer is received from the phy layer. 30 ? 28 rsvd r reserved. bits 30 ? 28 return 0s when read. 27 ? 24 rdaddr ru this field is the address of the register most recently received from the phy layer. 23 ? 16 rddata ru this field is the contents of a phy register that has been read. 15 rdreg rwu bit 15 is set to 1 by software to initiate a read request to a phy register and is cleared by hardware when the request has been sent. bits 14 (wrreg) and 15 (rdreg) must not both be set to 1 simultaneously. 14 wrreg rwu bit 14 is set to 1 by software to initiate a write request to a phy register and is cleared by hardware when the request has been sent. bits 14 (wrreg) and 15 (rdreg) must not both be set to 1 simultaneously. 13 ? 12 rsvd r reserved. bits 13 and 12 return 0s when read. 11 ? 8 regaddr r/w this field is the address of the phy register to be written or read. 7 ? 0 wrdata r/w this field is the data to be written to a phy register and is ignored for reads.
4 ? 30 4.34 isochronous cycle timer register the isochronous cycle timer register indicates the current cycle number and offset. when the TSB43AB21A device is cycle master, this register is transmitted with the cycle start message. when the TSB43AB21A device is not cycle master, this register is loaded with the data field in an incoming cycle start. in the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. see table 4 ? 26 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous cycle timer type rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous cycle timer type rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu default x x x x x x x x x x x x x x x x register: isochronous cycle timer offset: f0h type: read/write/update default: xxxx xxxxh table 4 ? 26. isochronous cycle timer register description bit field name type description 31 ? 25 cycleseconds rwu this field counts seconds [rollovers from bits 24 ? 12 (cyclecount field)] modulo 128. 24 ? 12 cyclecount rwu this field counts cycles [rollovers from bits 11 ? 0 (cycleoffset field)] modulo 8000. 11 ? 0 cycleoffset rwu this field counts 24.576-mhz clocks modulo 3072, that is, 125 s. if an external 8-khz clock configuration is being used, this field must be cleared to 0s at each tick of the external clock.
4 ? 31 4.35 asynchronous request filter high register the asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node ids. when a packet is destined for either the physical request context or the arrq context, the source node id is examined. if the bit corresponding to the node id is not set to 1 in this register, the packet is not acknowledged and the request is not queued. the node id comparison is done if the source node is on the same bus as the TSB43AB21A device. nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. see table 4 ? 27 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name asynchronous request filter high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asynchronous request filter high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: asynchronous request filter high offset: 100h set register 104h clear register type: read/set/clear default: 0000 0000h table 4 ? 27. asynchronous request filter high register description bit field name type description 31 asynreqallbuses rsc if bit 31 is set to 1, all asynchronous requests received by the TSB43AB21A device from nonlocal bus nodes are accepted. 30 asynreqresource62 rsc if bit 30 is set to 1 for local bus node number 62, asynchronous requests received by the TSB43AB21A device from that node are accepted. 29 asynreqresource61 rsc if bit 29 is set to 1 for local bus node number 61, asynchronous requests received by the TSB43AB21A device from that node are accepted. 28 asynreqresource60 rsc if bit 28 is set to 1 for local bus node number 60, asynchronous requests received by the TSB43AB21A device from that node are accepted. 27 asynreqresource59 rsc if bit 27 is set to 1 for local bus node number 59, asynchronous requests received by the TSB43AB21A device from that node are accepted. 26 asynreqresource58 rsc if bit 26 is set to 1 for local bus node number 58, asynchronous requests received by the TSB43AB21A device from that node are accepted. 25 asynreqresource57 rsc if bit 25 is set to 1 for local bus node number 57, asynchronous requests received by the TSB43AB21A device from that node are accepted. 24 asynreqresource56 rsc if bit 24 is set to 1 for local bus node number 56, asynchronous requests received by the TSB43AB21A device from that node are accepted. 23 asynreqresource55 rsc if bit 23 is set to 1 for local bus node number 55, asynchronous requests received by the TSB43AB21A device from that node are accepted. 22 asynreqresource54 rsc if bit 22 is set to 1 for local bus node number 54, asynchronous requests received by the TSB43AB21A device from that node are accepted. 21 asynreqresource53 rsc if bit 21 is set to 1 for local bus node number 53, asynchronous requests received by the TSB43AB21A device from that node are accepted. 20 asynreqresource52 rsc if bit 20 is set to 1 for local bus node number 52, asynchronous requests received by the TSB43AB21A device from that node are accepted. 19 asynreqresource51 rsc if bit 19 is set to 1 for local bus node number 51, asynchronous requests received by the TSB43AB21A device from that node are accepted.
4 ? 32 table 4 ? 27. asynchronous request filter high register description (continued) bit field name type description 18 asynreqresource50 rsc if bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the TSB43AB21A device from that node are accepted. 17 asynreqresource49 rsc if bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the TSB43AB21A device from that node are accepted. 16 asynreqresource48 rsc if bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the TSB43AB21A device from that node are accepted. 15 asynreqresource47 rsc if bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the TSB43AB21A device from that node are accepted. 14 asynreqresource46 rsc if bit 14 is set to 1 for local bus node number 46, asynchronous requests received by the TSB43AB21A device from that node are accepted. 13 asynreqresource45 rsc if bit 13 is set to 1 for local bus node number 45, asynchronous requests received by the TSB43AB21A device from that node are accepted. 12 asynreqresource44 rsc if bit 12 is set to 1 for local bus node number 44, asynchronous requests received by the TSB43AB21A device from that node are accepted. 11 asynreqresource43 rsc if bit 11 is set to 1 for local bus node number 43, asynchronous requests received by the TSB43AB21A device from that node are accepted. 10 asynreqresource42 rsc if bit 10 is set to 1 for local bus node number 42, asynchronous requests received by the TSB43AB21A device from that node are accepted. 9 asynreqresource41 rsc if bit 9 is set to 1 for local bus node number 41, asynchronous requests received by the TSB43AB21A device from that node are accepted. 8 asynreqresource40 rsc if bit 8 is set to 1 for local bus node number 40, asynchronous requests received by the TSB43AB21A device from that node are accepted. 7 asynreqresource39 rsc if bit 7 is set to 1 for local bus node number 39, asynchronous requests received by the TSB43AB21A device from that node are accepted. 6 asynreqresource38 rsc if bit 6 is set to 1 for local bus node number 38, asynchronous requests received by the TSB43AB21A device from that node are accepted. 5 asynreqresource37 rsc if bit 5 is set to 1 for local bus node number 37, asynchronous requests received by the TSB43AB21A device from that node are accepted. 4 asynreqresource36 rsc if bit 4 is set to 1 for local bus node number 36, asynchronous requests received by the TSB43AB21A device from that node are accepted. 3 asynreqresource35 rsc if bit 3 is set to 1 for local bus node number 35, asynchronous requests received by the TSB43AB21A device from that node are accepted. 2 asynreqresource34 rsc if bit 2 is set to 1 for local bus node number 34, asynchronous requests received by the TSB43AB21A device from that node are accepted. 1 asynreqresource33 rsc if bit 1 is set to 1 for local bus node number 33, asynchronous requests received by the TSB43AB21A device from that node are accepted. 0 asynreqresource32 rsc if bit 0 is set to 1 for local bus node number 32, asynchronous requests received by the TSB43AB21A device from that node are accepted.
4 ? 33 4.36 asynchronous request filter low register the asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node ids. other than filtering different node ids, this register behaves identically to the asynchronous request filter high register. see table 4 ? 28 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name asynchronous request filter low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asynchronous request filter low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: asynchronous request filter low offset: 108h set register 10ch clear register type: read/set/clear default: 0000 0000h table 4 ? 28. asynchronous request filter low register description bit field name type description 31 asynreqresource31 rsc if bit 31 is set to 1 for local bus node number 31, asynchronous requests received by the TSB43AB21A device from that node are accepted. 30 asynreqresource30 rsc if bit 30 is set to 1 for local bus node number 30, asynchronous requests received by the TSB43AB21A device from that node are accepted. 29 ? 2 asynreqresourcen rsc bits 29 through 2 (asynreqresourcen, where n = 29, 28, 27, , 2) follow the same pattern as bits 31 and 30. 1 asynreqresource1 rsc if bit 1 is set to 1 for local bus node number 1, asynchronous requests received by the TSB43AB21A device from that node are accepted. 0 asynreqresource0 rsc if bit 0 is set to 1 for local bus node number 0, asynchronous requests received by the TSB43AB21A device from that node are accepted.
4 ? 34 4.37 physical request filter high register the physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node ids. when a packet is destined for the physical request context, and the node id has been compared against the arrq registers, then the comparison is done again with this register. if the bit corresponding to the node id is not set to 1 in this register, the request is handled by the arrq context instead of the physical request context. the node id comparison is done if the source node is on the same bus as the TSB43AB21A device. nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. see table 4 ? 29 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name physical request filter high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name physical request filter high type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: physical request filter high offset: 110h set register 114h clear register type: read/set/clear default: 0000 0000h table 4 ? 29. physical request filter high register description bit field name type description 31 physreqallbusses rsc if bit 31 is set to 1, all asynchronous requests received by the TSB43AB21A device from nonlocal bus nodes are accepted. bit 31 is not cleared by a pci_rst . 30 physreqresource62 rsc if bit 30 is set to 1 for local bus node number 62, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 29 physreqresource61 rsc if bit 29 is set to 1 for local bus node number 61, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 28 physreqresource60 rsc if bit 28 is set to 1 for local bus node number 60, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 27 physreqresource59 rsc if bit 27 is set to 1 for local bus node number 59, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 26 physreqresource58 rsc if bit 26 is set to 1 for local bus node number 58, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 25 physreqresource57 rsc if bit 25 is set to 1 for local bus node number 57, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 24 physreqresource56 rsc if bit 24 is set to 1 for local bus node number 56, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 23 physreqresource55 rsc if bit 23 is set to 1 for local bus node number 55, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 22 physreqresource54 rsc if bit 22 is set to 1 for local bus node number 54, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 21 physreqresource53 rsc if bit 21 is set to 1 for local bus node number 53, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 20 physreqresource52 rsc if bit 20 is set to 1 for local bus node number 52, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 19 physreqresource51 rsc if bit 19 is set to 1 for local bus node number 51, physical requests received by the TSB43AB21A device from that node are handled through the physical request context.
4 ? 35 table 4 ? 29. physical request filter high register description (continued) bit field name type description 18 physreqresource50 rsc if bit 18 is set to 1 for local bus node number 50, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 17 physreqresource49 rsc if bit 17 is set to 1 for local bus node number 49, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 16 physreqresource48 rsc if bit 16 is set to 1 for local bus node number 48, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 15 physreqresource47 rsc if bit 15 is set to 1 for local bus node number 47, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 14 physreqresource46 rsc if bit 14 is set to 1 for local bus node number 46, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 13 physreqresource45 rsc if bit 13 is set to 1 for local bus node number 45, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 12 physreqresource44 rsc if bit 12 is set to 1 for local bus node number 44, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 11 physreqresource43 rsc if bit 11 is set to 1 for local bus node number 43, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 10 physreqresource42 rsc if bit 10 is set to 1 for local bus node number 42, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 9 physreqresource41 rsc if bit 9 is set to 1 for local bus node number 41, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 8 physreqresource40 rsc if bit 8 is set to 1 for local bus node number 40, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 7 physreqresource39 rsc if bit 7 is set to 1 for local bus node number 39, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 6 physreqresource38 rsc if bit 6 is set to 1 for local bus node number 38, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 5 physreqresource37 rsc if bit 5 is set to 1 for local bus node number 37, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 4 physreqresource36 rsc if bit 4 is set to 1 for local bus node number 36, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 3 physreqresource35 rsc if bit 3 is set to 1 for local bus node number 35, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 2 physreqresource34 rsc if bit 2 is set to 1 for local bus node number 34, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 1 physreqresource33 rsc if bit 1 is set to 1 for local bus node number 33, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 0 physreqresource32 rsc if bit 0 is set to 1 for local bus node number 32, physical requests received by the TSB43AB21A device from that node are handled through the physical request context.
4 ? 36 4.38 physical request filter low register the physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node ids. when a packet is destined for the physical request context and the node id has been compared against the asynchronous request filter registers, then the node id comparison is done again with this register. if the bit corresponding to the node id is not set to 1 in this register, the request is handled by the asynchronous request context instead of the physical request context. see table 4 ? 30 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name physical request filter low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name physical request filter low type rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: physical request filter low offset: 118h set register 11ch clear register type: read/set/clear default: 0000 0000h table 4 ? 30. physical request filter low register description bit field name type description 31 physreqresource31 rsc if bit 31 is set to 1 for local bus node number 31, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 30 physreqresource30 rsc if bit 30 is set to 1 for local bus node number 30, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 29 ? 2 physreqresourcen rsc bits 29 through 2 (physreqresourcen, where n = 29, 28, 27, , 2) follow the same pattern as bits 31 and 30. 1 physreqresource1 rsc if bit 1 is set to 1 for local bus node number 1, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 0 physreqresource0 rsc if bit 0 is set to 1 for local bus node number 0, physical requests received by the TSB43AB21A device from that node are handled through the physical request context. 4.39 physical upper bound register (optional register) the physical upper bound register is an optional register and is not implemented. this register returns all 0s when read. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name physical upper bound type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name physical upper bound type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: physical upper bound offset: 120h type: read-only default: 0000 0000h
4 ? 37 4.40 asynchronous context control register the asynchronous context control set/clear register controls the state and indicates status of the dma context. see table 4 ? 31 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name asynchronous context control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asynchronous context control type rscu r r rsu ru ru r r ru ru ru ru ru ru ru ru default 0 0 0 x 0 0 0 0 x x x x x x x x register: asynchronous context control offset: 180h set register [atrq] 184h clear register [atrq] 1a0h set register [atrs] 1a4h clear register [atrs] 1c0h set register [arrq] 1c4h clear register [arrq] 1e0h set register [arrs] 1e4h clear register [arrs] type: read/set/clear/update, read/set/update, read/update, read-only default: 0000 x0xxh table 4 ? 31. asynchronous context control register description bit field name type description 31 ? 16 rsvd r reserved. bits 31 ? 16 return 0s when read. 15 run rscu bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the TSB43AB21A device changes this bit only on a system (hardware) or software reset. 14 ? 13 rsvd r reserved. bits 14 and 13 return 0s when read. 12 wake rsu software sets bit 12 to 1 to cause the TSB43AB21A device to continue or resume descriptor processing. the TSB43AB21A device clears this bit on every descriptor fetch. 11 dead ru the TSB43AB21A device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). asynchronous contexts supporting out-of-order pipelining provide unique contextcontrol.dead functionality. see section 7.7 in the 1394 open host controller interface specification (revision 1.1) for more information. 10 active ru the TSB43AB21A device sets bit 10 to 1 when it is processing descriptors. 9 ? 8 rsvd r reserved. bits 9 and 8 return 0s when read. 7 ? 5 spd ru this field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts. this field is encoded as: 000 = 100m bits/sec 001 = 200m bits/sec 010 = 400m bits/sec all other values are reserved. 4 ? 0 eventcode ru this field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully.
4 ? 38 4.41 asynchronous context command pointer register the asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB21A device accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see section 4.40, asynchronous context control register ) to 1. see table 4 ? 32 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name asynchronous context command pointer type rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name asynchronous context command pointer type rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu rwu default x x x x x x x x x x x x x x x x register: asynchronous context command pointer offset: 18ch [atrq] 1ach [atrs] 1cch [arrq] 1ech [arrs] type: read/write/update default: xxxx xxxxh table 4 ? 32. asynchronous context command pointer register description bit field name type description 31 ? 4 descriptoraddress rwu contains the upper 28 bits of the address of a 16-byte aligned descriptor block. 3 ? 0 z rwu indicates the number of contiguous descriptors at the address pointed to by the descriptor address. if z is 0, it indicates that the descriptoraddress field (bits 31 ? 4) is not valid.
4 ? 39 4.42 isochronous transmit context control register the isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit dma contexts. the n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, , 7). see table 4 ? 33 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous transmit context control type rscu rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc rsc default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous transmit context control type rsc r r rsu ru ru r r ru ru ru ru ru ru ru ru default 0 0 0 x 0 0 0 0 x x x x x x x x register: isochronous transmit context control offset: 200h + (16 x n) set register 204h + (16 x n) clear register type: read/set/clear/update, read/set/clear, read/set/update, read/update, read-only default: xxxx x0xxh table 4 ? 33. isochronous transmit context control register description bit field name type description 31 cyclematchenable rscu when bit 31 is set to 1, processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cyclematch field (bits 30 ? 16). the cyclematch field (bits 30 ? 16) must match the low-order two bits of cycleseconds and the 13-bit cyclecount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. since the isochronous transmit dma controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. the effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 open host controller interface specification. once the context has become active, hardware clears this bit. 30 ? 16 cyclematch rsc this field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle timer register at ohci offset f0h (see section 4.34, isochronous cycle timer register ) cycleseconds field (bits 31 ? 25) and the cyclecount field (bits 24 ? 12). if bit 31 (cyclematchenable) is set to 1, this isochronous transmit dma context becomes enabled for transmits when the low-order two bits of the isochronous cycle timer register at ohci offset f0h cycleseconds field (bits 31 ? 25) and the cyclecount field (bits 24 ? 12) value equal this field (cyclematch) value. 15 run rsc bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the TSB43AB21A device changes this bit only on a system (hardware) or software reset. 14 ? 13 rsvd r reserved. bits 14 and 13 return 0s when read. 12 wake rsu software sets bit 12 to 1 to cause the TSB43AB21A device to continue or resume descriptor processing. the TSB43AB21A device clears this bit on every descriptor fetch. 11 dead ru the TSB43AB21A device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run) to 0. 10 active ru the TSB43AB21A device sets bit 10 to 1 when it is processing descriptors. 9 ? 8 rsvd r reserved. bits 9 and 8 return 0s when read. 7 ? 5 spd ru this field in not meaningful for isochronous transmit contexts. 4 ? 0 event code ru following an output_last* command, the error code is indicated in this field. possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. ? on an overflow for each running context, the isochronous transmit dma supports up to 7 cycle skips, when the following are true : 1. bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1. 2. bits 4 ? 0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout. 3. bit 24 (unrecoverableerror) in the interrupt event register at ohci offset 80h/84h (see section 4.21, interrupt event register ) is set to 1.
4 ? 40 4.43 isochronous transmit context command pointer register the isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB21A device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see section 4.42, isochronous transmit context control register) to 1. the isochronous transmit dma context command pointer can be read when a context is active. the n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, , 7). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous transmit context command pointer type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous transmit context command pointer type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x register: isochronous transmit context command pointer offset: 20ch + (16 x n) type: read-only default: xxxx xxxxh 4.44 isochronous receive context control register the isochronous receive context control set/clear register controls options, state, and status for the isochronous receive dma contexts. the n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). see table 4 ? 34 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive context control type rsc rsc rscu rsc rsc r r r r r r r r r r r default x x x x x 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive context control type rscu r r rsu ru ru r r ru ru ru ru ru ru ru ru default 0 0 0 x 0 0 0 0 x x x x x x x x register: isochronous receive context control offset: 400h + (32 x n) set register 404h + (32 x n) clear register type: read/set/clear/update, read/set/clear, read/set/update, read/update, read-only default: xx00 x0xxh table 4 ? 34. isochronous receive context control register description bit field name type description 31 bufferfill rsc when bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive buffer. when this bit is cleared, each received packet is placed in a single buffer. if bit 28 (multichanmode) is set to 1, this bit must also be set to 1. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 30 isochheader rsc when bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. the end of the packet is marked with a xferstatus in the first doublet, and a 16-bit timestamp indicating the time of the most recently received (or sent) cyclestart packet. when this bit is cleared, the packet header is stripped from received isochronous packets. the packet header, if received, immediately precedes the packet payload. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
4 ? 41 table 4 ? 34. isochronous receive context control register description (continued) bit field name type description 29 cyclematchenable rscu when bit 29 is set to 1 and the 13-bit cyclematch field (bits 24 ? 12) in the isochronous receive context match register (see section 4.46, isochronous receive context match register ) matches the 13-bit cyclecount field in the cyclestart packet, the context begins running. the effects of this bit, however, are impacted by the values of other bits in this register. once the context has become active, hardware clears this bit. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 28 multichanmode rsc when bit 28 is set to 1, the corresponding isochronous receive dma context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at ohci offset 70h/74h (see section 4.19, isochronous receive channel mask high register ) and isochronous receive channel mask low register at ohci offset 78h/7ch (see section 4.20, isochronous receive channel mask low register ). the isochronous channel number specified in the isochronous receive context match register (see section 4.46, isochronous receive context match register ) is ignored. when this bit is cleared, the isochronous receive dma context receives packets for the single channel specified in the isochronous receive context match register (see section 4.46, isochronous receive context match register ). only one isochronous receive dma context may use the isochronous receive channel mask registers (see sections 4.19, isochronous receive channel mask high register , and 4.20, isochronous receive channel mask low register ). if more than one isochronous receive context control register has this bit set, the results are undefined. the value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 27 dualbuffermode rsc when bit 27 is set to 1, receive packets are separated into first and second payload and streamed independently to the firstbuffer series and secondbuffer series as described in section 10.2.3 in the 1394 open host controller interface specification . also, when bit 27 is set to 1, both bits 28 (multichanmode) and 31 (bufferfill) are cleared to 0. the value of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1. 26 ? 16 rsvd r reserved. bits 26 ? 16 return 0s when read. 15 run rscu bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. the TSB43AB21A device changes this bit only on a system (hardware) or software reset. 14 ? 13 rsvd r reserved. bits 14 and 13 return 0s when read. 12 wake rsu software sets bit 12 to 1 to cause the TSB43AB21A device to continue or resume descriptor processing. the TSB43AB21A device clears this bit on every descriptor fetch. 11 dead ru the TSB43AB21A device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). 10 active ru the TSB43AB21A device sets bit 10 to 1 when it is processing descriptors. 9 ? 8 rsvd r reserved. bits 9 and 8 return 0s when read. 7 ? 5 spd ru this field indicates the speed at which the packet was received. 000 = 100m bits/sec 001 = 200m bits/sec 010 = 400m bits/sec all other values are reserved. 4 ? 0 event code ru for bufferfill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and evt_unknown. packets with data errors (either datalength mismatches or datacrc errors) and packets for which a fifo overrun occurred are backed out. for packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown.
4 ? 42 4.45 isochronous receive context command pointer register the isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB21A device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see section 4.44, isochronous receive context control register ) to 1. the n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive context command pointer type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive context command pointer type r r r r r r r r r r r r r r r r default x x x x x x x x x x x x x x x x register: isochronous receive context command pointer offset: 40ch + (32 x n) type: read-only default: xxxx xxxxh
4 ? 43 4.46 isochronous receive context match register the isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified synchronous value. the n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). see table 4 ? 35 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive context match type r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default x x x x 0 0 0 x x x x x x x x x bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive context match type r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x 0 x x x x x x x register: isochronous receive context match offset: 410ch + (32 x n) type: read/write, read-only default: xxxx xxxxh table 4 ? 35. isochronous receive context match register description bit field name type description 31 tag3 r/w if bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b. 30 tag2 r/w if bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b. 29 tag1 r/w if bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b. 28 tag0 r/w if bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b. 27 rsvd r reserved. bit 27 returns 0 when read. 26 ? 12 cyclematch r/w this field contains a 15-bit value corresponding to the two low-order bits of cycleseconds and the 13-bit cyclecount field in the cyclestart packet. if cyclematchenable (bit 29) in the isochronous receive context control register (see section 4.44, isochronous receive context control register ) is set to 1, this context is enabled for receives when the two low-order bits of the isochronous cycle timer register at ohci offset f0h (see section 4.34, isochronous cycle timer register ) cycleseconds field (bits 31 ? 25) and cyclecount field (bits 24 ? 12) value equal this field (cyclematch) value. 11 ? 8 sync r/w this 4-bit field is compared to the sync field of each isochronous packet for this channel when the command descriptor w field is set to 11b. 7 rsvd r reserved. bit 7 returns 0 when read. 6 tag1syncfilter r/w if bit 6 and bit 29 (tag1) are set to 1, packets with tag 01b are accepted into the context if the two most significant bits of the packet sync field are 00b. packets with tag values other than 01b are filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions. if this bit is cleared, this context matches on isochronous receive packets as specified in bits 28 ? 31 (tag0 ? tag3) with no additional restrictions. 5 ? 0 channelnumber r/w this 6-bit field indicates the isochronous channel number for which this isochronous receive dma context accepts packets.
4 ? 44
5 ? 1 5 ti extension registers the ti extension base address register provides a method of accessing memory-mapped ti extension registers. see section 3.10, ti extension base address register , for register bit field details. see table 5 ? 1 for the ti extension register listing. table 5 ? 1. ti extension register map register name offset reserved 00h ? a7fh isochronous receive dv enhancement set a80h isochronous receive dv enhancement clear a84h link enhancement control set a88h link enhancement control clear a8ch isochronous transmit context 0 timestamp offset a90h isochronous transmit context 1 timestamp offset a94h isochronous transmit context 2 timestamp offset a98h isochronous transmit context 3 timestamp offset a9ch isochronous transmit context 4 timestamp offset aa0h isochronous transmit context 5 timestamp offset aa4h isochronous transmit context 6 timestamp offset aa8h isochronous transmit context 7 timestamp offset aa8h 5.1 dv and mpeg2 timestamp enhancements the dv timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register located at pci offset f4h and are aliased in ti extension register space at offset a88h (set) and a8ch (clear). the dv and mpeg transmit enhancements are enabled separately by bits in the link enhancement control register located in pci configuration space at pci offset f4h. the link enhancement control register is also aliased as a set/clear register in ti extension space at offset a88h (set) and a8ch (clear). bit 8 (enab_dv_ts) of the link enhancement control register enables dv timestamp support. when enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the syt field of the cip once per dv frame. bit 10 (enab_mpeg_ts) of the link enhancement control register enables mpeg timestamp support. two mpeg time stamp modes are supported. the default mode calculates an initial delta that is added to the calculated timestamp in addition to a user-defined offset. the initial offset is calculated as the difference in the intended transmit cycle count and the cycle count field of the timestamp in the first tsp of the mpeg2 stream. the use of the initial delta can be controlled by bit 31 (disableinitialoffset) in the timestamp offset register (see section 5.5, timestamp offset register ). the mpeg2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control register located at pci offset f4h and aliased in ti extension register space at offset a88h (set) and a8ch (clear). when bit 10 (enab_mpeg_ts) is set to 1, the hardware applies the timestamp enhancements to isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a fmt field equal to 10h.
5 ? 2 5.2 isochronous receive digital video enhancements the dv frame synchronous and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 dv data that is received in the correct order to dv frame-sized data buffers described by several input_more descriptors (see 1394 open host controller interface specification , revision 1.1). this is accomplished by waiting for the start-of-frame packet in a dv stream before transferring the received isochronous stream into the memory buffer described by the input_more descriptors. this can improve the dv capture application performance by reducing the amount of processing overhead required to strip the cip header and copy the received packets into frame-sized buffers. the start of a dv frame is represented in the 1394 packet as a 16-bit pattern of 1fx7h (first byte 1fh and second byte x7h) received as the first two bytes of the third quadlet in a dv isochronous packet. 5.3 isochronous receive digital video enhancements register the isochronous receive digital video enhancements register enables the dv enhancements in the TSB43AB21A device. the bits in this register may only be modified when both the active (bit 10) and run (bit 15) bits of the corresponding context control register are 0. see table 5 ? 2 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name isochronous receive digital video enhancements type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name isochronous receive digital video enhancements type r r rsc rsc r r rsc rsc r r rsc rsc r r rsc rsc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: isochronous receive digital video enhancements offset: a80h set register a84h clear register type: read/set/clear, read-only default: 0000 0000h table 5 ? 2. isochronous receive digital video enhancements register description bit field name type description 31 ? 14 rsvd r reserved. bits 31 ? 14 return 0s when read. 13 dv_branch3 rsc when bit 13 is set to 1, the isochronous receive context 3 synchronizes reception to the dv frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by framebranch if a dv frame start tag is received out of place. this bit is only interpreted when bit 12 (cip_strip3) is set to 1 and bit 30 (isochheader) in the isochronous receive context control register at ohci offset 460h/464h (see section 4.44, isochronous receive context control register ) is cleared to 0. 12 cip_strip3 rsc when bit 12 is set to 1, the isochronous receive context 3 strips the first two quadlets of payload. this bit is only interpreted when bit 30 (isochheader) in the isochronous receive context control register at ohci offset 460h/464h (see section 4.44, isochronous receive context control register ) is cleared to 0. 11 ? 10 rsvd r reserved. bits 11 and 10 return 0s when read. 9 dv_branch2 rsc when bit 9 is set to 1, the isochronous receive context 2 synchronizes reception to the dv frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by framebranch if a dv frame start tag is received out of place. this bit is only interpreted when bit 8 (cip_strip2) is set to 1 and bit 30 (isochheader) in the isochronous receive context control register at ohci offset 440h/444h (see section 4.44, isochronous receive context control register ) is cleared to 0.
5 ? 3 table 5 ? 2. isochronous receive digital video enhancements register description (continued) bit field name type description 8 cip_strip2 rsc when bit 8 is set to 1, the isochronous receive context 2 strips the first two quadlets of payload. this bit is only interpreted when bit 30 (isochheader) in the isochronous receive context control register at ohci offset 440h/444h (see section 4.44, isochronous receive context control register ) is cleared to 0. 7 ? 6 rsvd r reserved. bits 7 and 6 return 0s when read. 5 dv_branch1 rsc when bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the dv frame start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by framebranch if a dv frame start tag is received out of place. this bit is only interpreted when bit 4 (cip_strip1) is set to 1 and bit 30 (isochheader) in the isochronous receive context control register at ohci offset 420h/424h (see section 4.44, isochronous receive context control register ) is cleared to 0. 4 cip_strip1 rsc when bit 4 is set to 1, the isochronous receive context 1 strips the first two quadlets of payload. this bit is only interpreted when bit 30 (isochheader) in the isochronous receive context control register at ohci offset 420h/424h (see section 4.44, isochronous receive context control register ) is cleared to 0. 3 ? 2 rsvd r reserved. bits 3 and 2 return 0s when read. 1 dv_branch0 rsc when bit 1 is set to 1, the isochronous receive context 0 synchronizes reception to the dv frame start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by framebranch if a dv frame start tag is received out of place. this bit is only interpreted when bit 0 (cip_strip0) is set to 1 and bit 30 (isochheader) in the isochronous receive context control register at ohci offset 400h/404h (see section 4.44, isochronous receive context control register ) is cleared to 0. 0 cip_strip0 rsc when bit 0 is set to 1, the isochronous receive context 0 strips the first two quadlets of payload. this bit is only interpreted when bit 30 (isochheader) in the isochronous receive context control register at ohci offset 400h/404h (see section 4.44, isochronous receive context control register ) is cleared to 0.
5 ? 4 5.4 link enhancement register this register is a memory-mapped set/clear register that is an alias of the link enhancement control register at pci offset f4h. these bits may be initialized by software. some of the bits may also be initialized by a serial eeprom, if one is present, as noted in the bit descriptions below. if the bits are to be initialized by software, the bits must be initialized prior to setting bit 19 (lps) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ). see table 5 ? 3 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name link enhancement type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name link enhancement type rsc r rsc rsc r rsc r rsc rsc r r r r r rsc r default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 register: link enhancement offset: a88h set register a8ch clear register type: read/set/clear, read-only default: 0000 0000h table 5 ? 3. link enhancement register description bit field name type description 31 ? 16 rsvd r reserved. bits 31 ? 16 return 0s when read. 15 dis_at_pipeline rsc disable at pipelining. when bit 15 is set to 1, out-of-order at pipelining is disabled. 14 rsvd r reserved. 13 ? 12 atx_thresh rsc this field sets the initial at threshold value, which is used until the at fifo is underrun. when the TSB43AB21A device retries the packet, it uses a 2k-byte threshold, resulting in a store-and-forward operation. 00 = threshold ~ 2k bytes resulting in a store-and-forward operation 01 = threshold ~ 1.7k bytes (default) 10 = threshold ~ 1k bytes 11 = threshold ~ 512 bytes these bits fine-tune the asynchronous transmit threshold. for most applications the 1.7k-byte threshold is optimal. changing this value may increase or decrease the 1394 latency depending on the average pci bus latency. setting the at threshold to 1.7k, 1k, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the fifo. if the packet to be transmitted is larger than the at threshold, the remaining data must be received before the at fifo is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. as a result, the link then commences store-and-forward operation. wait until it has the complete packet in the fifo before retransmitting it on the second attempt, to ensure delivery. an at threshold of 2k results in store-and-forward operation, which means that asynchronous data will not be transmitted until an end-of-packet token is received. restated, setting the at threshold to 2k results in only complete packets being transmitted. note that this device always uses store-and-forward when the asynchronous transmit retries register at ohci offset 08h (see section 4.3, asynchronous transmit retries register ) is cleared. 11 rsvd r reserved. bit 11 returns 0 when read. 10 enab_mpeg_ts rsc enable mpeg timestamp enhancements. when bit 10 is set to 1, the enhancement is enabled for mpeg transmit streams (fmt = 20h). 9 rsvd r reserved. bit 9 returns 0 when read. 8 enab_dv_ts rsc enable dv cip timestamp enhancement. when bit 8 is set to 1, the enhancement is enabled for dv cip transmit streams (fmt = 00h).
5 ? 5 table 5 ? 3. link enhancement register description (continued) 7 enab_unfair rsc enable asynchronous priority requests. iohci-lynx ? compatible. setting bit 7 to 1 enables the link to respond to requests with priority arbitration. it is recommended that this bit be set to 1. 6 rsvd r this bit is not assigned in the TSB43AB21A follow-on products, since this bit location loaded by the serial eeprom from the enhancements field corresponds to bit 23 (programphyenable) in the host controller control register at ohci offset 50h/54h (see section 4.16, host controller control register ). 5 ? 2 rsvd r reserved. bits 5 ? 2 return 0s when read. 1 enab_accel rsc enable acceleration enhancements. iohci-lynx ? compatible. when bit 1 is set to 1, the phy layer is notified that the link supports the ieee std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. it is recommended that this bit be set to 1. 0 rsvd r reserved. bit 0 returns 0 when read. 5.5 timestamp offset register the value of this register is added as an offset to the cycle timer value when using the mpeg, dv, and cip enhancements. a timestamp offset register is implemented per isochronous transmit context. the n value following the offset indicates the context number (n = 0, 1, 2, 3, , 7). these registers are programmed by software as appropriate. see table 5 ? 4 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name timestamp offset type r/w r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name timestamp offset type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: timestamp offset offset: a90h + (4 x n) type: read/write, read-only default: 0000 0000h table 5 ? 4. timestamp offset register description bit field name type description 31 disableinitialoffset r/w bit 31 disables the use of the initial timestamp offset when the mpeg2 enhancements are enabled. a value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not be applied to the calculated timestamp. this bit has no meaning for the dv timestamp enhancements. 30 ? 25 rsvd r reserved. bits 30 ? 25 return 0s when read. 24 ? 12 cyclecount r/w this field adds an offset to the cycle count field in the timestamp when the dv or mpeg2 enhancements are enabled. the cycle count field is incremented modulo 8000; therefore, values in this field must be limited between 0 and 7999. 11 ? 0 cycleoffset r/w this field adds an offset to the cycle offset field in the timestamp when the dv or mpeg2 enhancements are enabled. the cycle offset field is incremented modulo 3072; therefore, values in this field must be limited between 0 and 3071.
5 ? 6
6 ? 1 6 serial eeprom interface the TSB43AB21A device provides a serial bus interface to initialize the guid registers and a few pci configuration registers through a serial eeprom. the TSB43AB21A device communicates with the serial eeprom via the 2-wire serial interface. after power up the serial interface initializes the locations listed in table 6 ? 1. while the TSB43AB21A device accesses the serial eeprom, all incoming pci slave accesses are terminated with retry status. table 6 ? 2 shows the serial eeprom memory map required for initializing the TSB43AB21A registers. note: if an eeprom is implemented in the design, byte offsets 00h ? 16h must be programmed. an unprogrammed eeprom defaults to all 1s, which can adversely impact device operation. table 6 ? 1. registers and bits loadable through serial eeprom eeprom byte offset ohci/pci configuration offset register name register bits loaded from eeprom 00h pci register (3eh) pci maximum latency, pci minimum grant 15 ? 0 01h pci register (2dh) vendor identification 15 ? 0 03h pci register (2ch) subsystem identification 15 ? 0 05h (bit 6) ohci register (50h) host controller control 23 05h pci register (f4h) link enhancement control 7, 6, 1 06h ohci register (04h) guid rom 7 ? 0 07h ? 0ah ohci register (24h) guid high 31 ? 0 0bh ? 0eh ohci register (28h) guid low 31 ? 0 10h pci register (f4h) link enhancement control 15 ? 12 11h ? 12h pci register (f0h) miscellaneous configuration ? 15, 4 14h pci register (28h) cardbus cis pointer 7 ? 3 16h pci register (ech) pci phy control ? 7 ? 0 ? bits 2 ? 0 at eeprom byte offset 11h must be programmed to 000b to ensure proper functioning. by default, unprogrammed eeprom bits are 1. ? bits 6 ? 4 and 2 ? 0 at eeprom byte offset 16h must be programmed to 0 to ensure proper functioning. bit 3 must be programmed to 1. if cna functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.
6 ? 2 table 6 ? 2. serial eeprom map eeprom byte address byte description 00 pci maximum latency (0h) pci_minimum grant (0h) 01 pci vendor id 02 pci vendor id (msbyte) 03 pci subsystem id (lsbyte) 04 pci subsystem id (msbyte) 05 [7] link_enhancement control.enab_unfair [6] hccontrol. programphy enable [5 ? 3] rsvd [2] rsvd ? [1] link_enhancement control.enab_accel [0] rsvd 06 [7 ? 6] rsvd mini rom address [4 ? 3] rsvd 07 guid high (lsbyte 0) 08 guid high (byte 1) 09 guid high (byte 2) 0a guid high (msbyte 3) 0b guid low (lsbyte 0) 0c guid low (byte 1) 0d guid low (byte 2) 0e guid low (msbyte 3) 0f checksum 10 ? [15] dis_at_pipeline [14] rsvd [13 ? 12] atx threshold [11 ? 8] rsvd 11 [7 ? 5] rsvd [4] disable target abort [3 ? 0] rsvd 12 [15] pme d3 cold [14 ? 8] rsvd 13 [7 ? 0] rsvd 14 [7 ? 3] cis_offset [2 ? 0] rsvd 15 rsvd 16 ? [7] cna out enable [6 ? 4] rsvd [3] rsvd [2 ? 0] rsvd 17 ? 1f rsvd ? bit 2 at eeprom byte offset 05h must be programmed to 0b. ? bit 14 must be programmed to 0 for normal operation. bits 2 ? 0 at eeprom byte offset 11h must be programmed to 000b to ensure proper functioning. by default, unprogrammed eeprom bits are 1. ? bits 6 ? 4 and 2 ? 0 at eeprom byte offset 16h must be programmed to 0 to ensure proper functioning. bit 3 must be programmed to 1. if cna functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.
7 ? 1 7 phy register configuration there are 16 accessible internal registers in the TSB43AB21A device. the configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. the selected page is set in base register 7h. 7.1 base registers table 7 ? 1 shows the configuration of the base registers, and table 7 ? 2 shows the corresponding field descriptions. the base register field definitions are unaffected by the selected page number. a reserved register or register field (marked as reserved in the following register configuration tables) is read as 0, but is subject to future usage. all registers in address pages 2 through 6 are reserved. table 7 ? 1. base register configuration address bit position address 0 1 2 3 4 5 6 7 0000 physical id r cps 0001 rhb ibr gap_count 0010 extended (111b) reserved total_ports (0001b) 0011 max_speed (010b) reserved delay (0000b) 0100 lctrl c jitter (000b) pwr_class 0101 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 reserved 0111 page_select reserved port_select
7 ? 2 table 7 ? 2. base register field descriptions field size type description physical id 6 r this field contains the physical address id of this node determined during self-id. the physical id is invalid after a bus reset until self-id has completed as indicated by an unsolicited register-0 status transfer. r 1 r root. this bit indicates that this node is the root node. the r bit is cleared to 0 by bus reset and is set to 1 during tree-id if this node becomes root. cps 1 r cable-power-status. this bit indicates the state of the cps input terminal. the cps terminal is normally tied to serial bus cable power through a 400-k ? resistor. a 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. rhb 1 r/w root-holdoff bit. this bit instructs the phy layer to attempt to become root after the next bus reset. the rhb bit is cleared to 0 by a system (hardware) reset and is unaffected by a bus reset. ibr 1 r/w initiate bus reset. this bit instructs the phy layer to initiate a long (166 s) bus reset at the next opportunity. any receive or transmit operation in progress when this bit is set will complete before the bus reset is initiated. the ibr bit is cleared to 0 after a system (hardware) reset or a bus reset. gap_count 6 r/w arbitration gap count. this value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. the gap count can be set either by a write to the register, or by reception or transmission of a phy_config packet. the gap count is reset to 3fh by system (hardware) reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the phy register or by a phy_config packet). extended 3 r extended register definition. for the TSB43AB21A device, this field is 111b, indicating that the extended register set is implemented. total_ports 4 r number of ports. this field indicates the number of ports implemented in the phy layer. for the TSB43AB21A device this field is 1. max_speed 3 r phy speed capability. for the TSB43AB21A phy layer this field is 010b, indicating s400 speed capability. delay 4 r phy repeater data delay. this field indicates the worst case repeater data delay of the phy layer, expressed as 144+(delay 20) ns. for the TSB43AB21A device this field is 0. lctrl 1 r/w link-active status control. this bit controls the active status of the llc as indicated during self-id. the logical and of this bit and the lps active status is replicated in the l field (bit 9) of the self-id packet. the llc is considered active only if both the lps input is active and the lctrl bit is set. the lctrl bit provides a software controllable means to indicate the llc active/status in lieu of using the lps input. the lctrl bit is set to 1 by a system (hardware) reset and is unaffected by a bus reset. note: the state of the phy-llc interface is controlled solely by the lps input, regardless of the state of the lctrl bit. if the phy-llc interface is operational as determined by the lps input being active, received packets and status information continue to be presented on the interface, and any requests indicated on the lreq input are processed, even if the lctrl bit is cleared to 0. c 1 r/w contender status. this bit indicates that this node is a contender for the bus or isochronous resource manager. this bit is replicated in the c field (bit 20) of the self-id packet. jitter 3 r phy repeater jitter. this field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (jitter+1) 20 ns. for the TSB43AB21A device, this field is 0. pwr_class 3 r/w node power class. this field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21 ? 23) of the self-id packet. this field is reset to the state specified by the pc0 ? pc2 input terminals upon a system (hardware) reset and is unaffected by a bus reset. see table 7 ? 9. watchdog 1 r/w watchdog enable. this bit, if set to 1, enables the port event interrupt (port_event) bit to be set whenever resume operations begin on the port. this bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset.
7 ? 3 table 7 ? 2. base register field descriptions (continued) field size type description isbr 1 r/w initiate short arbitrated bus reset. this bit, if set to 1, instructs the phy layer to initiate a short (1.3 s) arbitrated bus reset at the next opportunity. this bit is cleared to 0 by a bus reset. note: legacy ieee std 1394-1995 compliant phy layers can not be capable of performing short bus resets. therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. loop 1 r/w loop detect. this bit is set to 1 when the arbitration controller times out during tree-id start and may indicate that the bus is configured in a loop. this bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. if the loop and watchdog bits are both set and the llc is or becomes inactive, the phy layer activates the llc to service the interrupt. note: if the network is configured in a loop, only those nodes which are part of the loop generate a configuration-timeout interrupt. all other nodes instead time out waiting for the tree-id and/or self-id process to complete and then generate a state time-out interrupt and bus-reset. pwr_fail 1 r/w cable power failure detect. this bit is set to 1 whenever the cps input transitions from high to low indicating that cable power may be too low for reliable operation. this bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. timeout 1 r/w state time-out interrupt. this bit indicates that a state time-out has occurred (which also causes a bus reset to occur). this bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. port_event 1 r/w port event detect. this bit is set to 1 upon a change in the bias (unless disabled) connected, disabled, or fault bits for the port if the port interrupt enable (int_enable) bit is set. additionally, if the watchdog bit is set, the port_event bit is set to 1 at the start of resume operations on the port. this bit is cleared to 0 by system (hardware) reset or by writing a 1 to this register bit. enab_accel 1 r/w enable accelerated arbitration. this bit enables the phy layer to perform the various arbitration acceleration enhancements defined in ieee std 1394a-2000 (ack-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). this bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. enab_multi 1 r/w enable multispeed concatenated packets. this bit enables the phy layer to transmit concatenated packets of differing speeds in accordance with the protocols defined in ieee std 1394a-2000. this bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. page_select 3 r/w page_select. this field selects the register page to use when accessing register addresses 8 through 15. this field is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. port_select 4 r/w port_select. this field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). ports are numbered starting at 0. this field is cleared to 0 by system (hardware) reset and is unaffected by bus reset. if the port_select field is programmed to a value that is not supported (for example, the TSB43AB21A device only supports port 0), all registers in the port status page read 0.
7 ? 4 7.2 port status register the port status page provides access to configuration and status information for the port. the port is selected by writing 0 to the page_select field and to the port_select field in base register 7. table 7 ? 3 shows the configuration of the port status page registers and table 7 ? 4 shows the corresponding field descriptions. if the selected port is not implemented, all registers in the port status page are read as 0. table 7 ? 3. page 0 (port status) register configuration bit position address 0 1 2 3 4 5 6 7 1000 astat bstat ch con bias dis 1001 peer_speed int_enable fault reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 7 ? 4. page 0 (port status) register field descriptions field size type description astat 2 r tpa line state. this field indicates the tpa line state of the selected port, encoded as follows: code arb value 11 z 10 0 01 1 00 invalid bstat 2 r tpb line state. this field indicates the tpb line state of the selected port. this field has the same encoding as the astat field. ch 1 r child/parent status. a 1 indicates that the selected port is a child port. a 0 indicates that the selected port is the parent port. a disconnected, disabled, or suspended port is reported as a child port. the ch bit is invalid after a bus reset until tree-id has completed. con 1 r debounced port connection status. this bit indicates that the selected port is connected. the connection must be stable for the debounce time of approximately 341 ms for the con bit to be set to 1. the con bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. note: the con bit indicates that the port is physically connected to a peer phy device, but the port is not necessarily active. bias 1 r debounced incoming cable bias status. a 1 indicates that the selected port is detecting incoming cable bias. the incoming cable bias must be stable for the debounce time of 52 s for the bias bit to be set to 1. dis 1 r/w port disabled control. if the dis bit is set to 1, the selected port is disabled. the dis bit is cleared to 0 by system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). the dis bit is not affected by bus reset. peer_speed 3 r port peer speed. this field indicates the highest speed capability of the peer phy device connected to the selected port, encoded as follows: code peer speed 000 s100 001 s200 010 s400 011 ? 111 invalid the peer_speed field is invalid after a bus reset until self-id has completed. note: peer speed codes higher than 010b (s400) are defined in ieee std 1394a-2000. however, the TSB43AB21A device is only capable of detecting peer speeds up to s400.
7 ? 5 table 7 ? 4. page 0 (port status) register field descriptions (continued) field size type description int_enable 1 r/w port event interrupt enable. when the int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (port_event) bit and notifies the link. this bit is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. fault 1 r/w fault. this bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. a resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. a suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. writing 1 to this bit clears the fault bit to 0. this bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. 7.3 vendor identification register the vendor identification page identifies the vendor/manufacturer and compliance level. the page is selected by writing 1 to the page_select field in base register 7. table 7 ? 5 shows the configuration of the vendor identification page, and table 7 ? 6 shows the corresponding field descriptions. table 7 ? 5. page 1 (vendor id) register configuration bit position address 0 1 2 3 4 5 6 7 1000 compliance 1001 reserved 1010 vendor_id[0] 1011 vendor_id[1] 1100 vendor_id[2] 1101 product_id[0] 1110 product_id[1] 1111 product_id[2] table 7 ? 6. page 1 (vendor id) register field descriptions field size type description compliance 8 r compliance level. for the TSB43AB21A device this field is 01h, indicating compliance with ieee std 1394a-2000. vendor_id 24 r manufacturer ? s organizationally unique identifier (oui). for the TSB43AB21A device this field is 08 0028h (texas instruments) (the msb is at register address 1010b). product_id 24 r product identifier. for the TSB43AB21A device this field is 42 4499h (the msb is at register address 1101b).
7 ? 6 7.4 vendor-dependent register the vendor-dependent page provides access to the special control features of the TSB43AB21A device, as well as to configuration and status information used in manufacturing test and debug. this page is selected by writing 7 to the page_select field in base register 7. table 7 ? 7 shows the configuration of the vendor-dependent page, and table 7 ? 8 shows the corresponding field descriptions. table 7 ? 7. page 7 (vendor-dependent) register configuration bit position address 0 1 2 3 4 5 6 7 1000 npa reserved link_speed 1001 reserved for test 1010 reserved for test 1011 reserved for test 1100 reserved for test 1101 reserved for test 1110 reserved for test 1111 reserved for test table 7 ? 8. page 7 (vendor-dependent) register field descriptions field size type description npa 1 r/w null-packet actions flag. this bit instructs the phy layer to not clear fair and priority requests when a null packet is received with arbitration acceleration enabled. if this bit is set to 1, fair and priority requests are cleared only when a packet of more than 8 bits is received; ack packets (exactly 8 data bits), null packets (no data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. if this bit is cleared to 0, fair and priority requests are cleared when any non-ack packet is received, including null packets or malformed packets of less than 8 bits. this bit is cleared to 0 by system (hardware) reset and is unaffected by bus reset. link_speed 2 r/w link speed. this field indicates the top speed capability of the attached llc. encoding is as follows: code speed 00 s100 01 s200 10 s400 11 illegal this field is replicated in the sp field of the self-id packet to indicate the speed capability of the node (phy and llc in combination). however, this field does not affect the phy speed capability indicated to peer phys during self-id; the TSB43AB21A phy layer identifies itself as s400 capable to its peers regardless of the value in this field. this field is set to 10b (s400) by system (hardware) reset and is unaffected by bus reset.
7 ? 7 7.5 power-class programming the pc0 ? pc2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21 ? 23) of the transmitted self-id packet. table 7 ? 9 shows the descriptions of the various power classes. the default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the pwr_class field in register 4. table 7 ? 9. power class descriptions pc0 ? pc2 description 000 node does not need power and does not repeat power. 001 node is self-powered and provides a minimum of 15 w to the bus. 010 node is self-powered and provides a minimum of 30 w to the bus. 011 node is self-powered and provides a minimum of 45 w to the bus. 100 node may be powered from the bus and is using up to 3 w. no additional power is needed to enable the link. 101 reserved 110 node is powered from the bus and uses up to 3 w. an additional 3 w is needed to enable the link. 111 node is powered from the bus and uses up to 3 w. an additional 7 w is needed to enable the link.
7 ? 8
8 ? 1 8 application information 8.1 phy port cable connection tpa+ tpa ? tpb+ tpb ? cable port cps tpbias 56 ? 56 ? 56 ? 56 ? 5 k ? 1 f 400 k ? 220 pf (see note a) TSB43AB21A cable power pair cable pair a cable pair b outer shield termination note a: ieee std 1394-1995 calls for a 250-pf capacitor, which is a nonstandard component value. a 220-pf capacitor is recommend ed. figure 8 ? 1. tp cable connections
8 ? 2 1 m ? 0.001 f 0.01 f outer cable shield chassis ground figure 8 ? 2. typical compliant dc isolated outer shield termination outer cable shield chassis ground figure 8 ? 3. non-dc isolated outer shield termination 8.2 crystal selection the TSB43AB21A device is designed to use an external 24.576-mhz crystal connected between the xi and xo pins to provide the reference for an internal oscillator circuit. this oscillator in turn drives a pll circuit that generates the various clocks required for transmission and resynchronization of data at the s100 through s400 media data rates. a variation of less than 100 ppm from nominal for the media data rates is required by ieee std 1394-1995. adjacent phys may therefore have a difference of up to 200 ppm from each other in their internal clocks, and phy devices must be able to compensate for this difference over the maximum packet length. large clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. the following are some typical specifications for crystals used with the phys from ti in order to achieve the required frequency accuracy and stability: ? crystal mode of operation: fundamental ? frequency tolerance @ 25 c: total frequency variation for the complete circuit is 100 ppm. a crystal with 30 ppm frequency tolerance is recommended for adequate margin. ? frequency stability (over temperature and age): a crystal with 30 ppm frequency stability is recommended for adequate margin. note: the total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. for example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. crystal aging also contributes to the frequency variation. ? load capacitance: for parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also board layout and circuit. it is recommended that load capacitors with a maximum of 5% tolerance be used.
8 ? 3 for example, load capacitors (c9 and c10 in figure 8 ? 4) of 16 pf each were appropriate for the layout of the TSB43AB21A evaluation module (evm), which uses a crystal specified for 12-pf loading. the load specified for the crystal includes the load capacitors (c9 and c10), the loading of the phy pins (c phy ), and the loading of the board itself (c bd ). the value of c phy is typically about 1 pf, and c bd is typically 0.8 pf per centimeter of board etch; a typical board can have 3 pf to 6 pf or more. the load capacitors c9 and c10 combine as capacitors in series so that the total load capacitance is: c l c9 c10 c9 c10 c phy c bd x1 24.576 mhz i s x1 c phy + c bd x0 c10 c9 figure 8 ? 4. load capacitance for the TSB43AB21A phy the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency, minimizing noise introduced into the phy phase-lock loop, and minimizing any emissions from the circuit. the crystal and two load capacitors must be considered as a unit during layout. the crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. varying the size of the capacitors may help in this. minimizing the loop area minimizes the effect of the resonant current (is) that flows in this resonant circuit. this layout unit (crystal and load capacitors) must then be placed as close as possible to the phy x1 and x0 pins to minimize etch lengths, as shown in figure 8 ? 5. c9 c10 x1 for more details on crystal selection, see application report slla051 available from the ti website: http://www.ti.com/sc/1394. figure 8 ? 5. recommended crystal and capacitor layout 8.3 bus reset in the TSB43AB21A device, the initiate bus reset (ibr) bit may be set to 1 in order to initiate a bus reset and initialization sequence. the ibr bit is located in phy register 1, along with the root-holdoff bit (rhb) and gap_count field, as required by ieee std 1394a-2000. therefore, whenever the ibr bit is written, the rhb and gap_count are also written. the rhb and gap_count may also be updated by phy-config packets. the TSB43AB21A device is ieee 1394a-2000 compliant, and therefore both the reception and transmission of phy-config packets cause the rhb and gap_count to be loaded, unlike older ieee 1394-1995 compliant phy devices which decode only received phy-config packets. the gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the gap_count, either by a write to phy register 1 or by a phy-config packet. this mechanism allows a phy-config
8 ? 4 packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their rhbs and gap_count values, without having the gap_count set back to 63 by the bus reset. the subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap_count of each node to be set to 63. note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the ibr bit, all other nodes on the bus have their gap_count values set to 63, while this node gap_count remains set to the value just loaded by the write to phy register 1. therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the ibr bit, rhb, and gap_count in phy register 1: ? following the transmission of a phy-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their rhbs and gap_count values and to ensure that a subsequent new connection to the bus causes the gap_count to be set to 63 on all nodes in the bus. if this bus reset is initiated by setting the ibr bit to 1, the rhb and gap_count field must also be loaded with the correct values consistent with the just transmitted phy-config packet. in the TSB43AB21A device, the rhb and gap_count are updated to their correct values upon the transmission of the phy-config packet, so these values may first be read from register 1 and then rewritten. ? other than to initiate the bus reset, which must follow the transmission of a phy-config packet, whenever the ibr bit is set to 1 in order to initiate a bus reset, the gap_count value must also be set to 63 so as to be consistent with other nodes on the bus, and the rhb must be maintained with its current value. ? the phy register 1 must not be written to except to set the ibr bit. the rhb and gap_count must not be written without also setting the ibr bit to 1. 8.4 emi guidelines for electromagnetic interference (emi) guidelines and recommendations send a request via e-mail to 1394 ? emi@list.ti.com.
9 ? 1 9 electrical characteristics 9.1 absolute maximum ratings over operating temperature ranges ? supply voltage range: reg18 ? 0.2 v to 2.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . av dd ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv dd ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pllv dd ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ddp ? 0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range for pci, v i , phy, and miscellaneous ? 0.5 to v dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range for pci, v o , phy, and miscellaneous ? 0.5 to v dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v dd ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v dd ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrostatic discharge (see note 3) hbm: 2 kv, mm: 200 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature, t a :TSB43AB21A 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSB43AB21Ai ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditio ns is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies to external input and bidirectional buffers. for 5-v tolerant use v i > v ddi . for pci use v i > v ddp . 2. applies to external output and bidirectional buffers. for 5-v tolerant use v o > v ddi . for pci use v o > v ddp . 3. hbm is human body model, mm is machine model. dissipation rating table package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating t a = 85 c power rating pdt ? 1.116 w 0.013 w/ c 0.563 w 0.336 w pdt 0.967 w 0.009 w/ c 0.523 w 0.427 w ? standard jedec high-k board standard jedec low-k board
9 ? 2 9.2 recommended operating conditions test condition min nom max unit reg18 1.6 1.8 2 v core voltage, av dd 3 3.3 3.6 v core voltage, dv dd 3 3.3 3.6 v core voltage, pllv dd 2.7 3 3.6 v output voltage, v o ttl and lvcmos terminals 0 dv dd v pci i/o clampin g volta g e, v ddp = 3.3 v 3 3.3 3.6 v pci i/o clam ing voltage , v ddp v ddp = 5 v 4.5 5 5.5 v pci 3.3 v 0.475 dv dd dv dd pci 5 v 2 v ddp high-level input voltage, v ih ? pc(0 ? 2) 0.7 dv dd dv dd v high level in ut voltage, v ih g_rst 0.6 dv dd dv dd miscellaneous ? 2 v ddp pci 3.3 v 0 0.325 dv dd pci 5 v 0 0.8 low-level input voltage, v il ? pc(0 ? 2) 0 0.2 dv dd v low level in ut voltage, v il g_rst 0 0.3 dv dd miscellaneous ? 0 0.8 input voltage v pci 3.3 v 0 dv dd v input voltage, v i miscellaneous ? 0 v ddp v output voltage v o pci 3.3 v 0 dv dd v output voltage, v o miscellaneous ? 0 dv dd v input transition time (t r and t f ), t t pci 0 6 ns operatin g free-air r 70 82 c/w t a = 70 c 99.3 c o erating free air temperature, t a r ja = 70.82 c/w t a = 85 c 110.5 c output current, i o tpbias outputs ? 5.6 1.3 ma differential input voltage v cable inputs, during data reception 118 260 mv differential input voltage, v id cable inputs, during arbitration 168 265 mv common-mode input volta g e, tpb cable inputs, source power node 0.4706 2.515 v common mode in ut voltage , v ic tpb cable inputs, nonsource power node 0.4706 2.015 ? v 128-pdt hi g h-k jedec board , t a = 70 c 96.8 c maximum junction 128 - pdt high - k jedec board , r ja = 74.6 c/w, p d = 0.36 w t a = 85 c 111.9 c maximum junction temperature, t j 128-pdt low-k jedec board , t a = 70 c 106.4 c j 128 - pdt low - k jedec board , r ja = 101.3 c/w, p d = 0.36 w t a = 85 c 121.5 c power up reset time, t pu g_rst input 2 ms tpa, tpb cable inputs, s100 operation 1.08 receive input jitter tpa, tpb cable inputs, s200 operation 0.5 ns receive in ut jitter tpa, tpb cable inputs, s400 operation 0.315 ns ? applies to external inputs and bidirectional buffers without hysteresis. ? miscellaneous terminals are: gpio2 (90), gpio3 (89), sda (92), scl (91). applies to external output buffers. ? for a node that does not source power; see section 4.2.2.2 in ieee std 1394a-2000.
9 ? 3 recommended operating conditions (continued) test condition min nom max unit riit between tpa and tpb cable inputs, s100 operation 0.8 receive input skew between tpa and tpb cable inputs, s200 operation 0.55 ns s k ew between tpa and tpb cable inputs, s400 operation 0.5 9.3 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter operation test conditions min max unit pci i oh = ? 0.5 ma 0.9 dv dd v oh high-level output voltage pci i oh = ? 2 ma 2.4 v v oh high level out ut voltage miscellaneous ? i oh = ? 4 ma dv dd ? 0.6 v pci i ol = 1.5 ma 0.1 dv dd v ol low-level output voltage pci i ol = 6 ma 0.55 v v ol low level out ut voltage miscellaneous ? i ol = 4 ma 0.5 v i oz 3-state output high-impedance output pins 3.6 v v o = dv dd or gnd 20 a i low level input current input pins 3.6 v v i = gnd 20 a i il low-level input current i/o pins ? 3.6 v v i = gnd 20 a i ih high level in p ut current pci ? 3.6 v v i = dv dd 20 a i ih high-level input current others ? 3.6 v v i = dv dd 20 a ? for i/o terminals, input leakage (i il and i ih ) includes i oz of the disabled output. ? miscellaneous terminals are: gpio2 (90), gpio3 (89), sda (92), scl (91).
9 ? 4 9.4 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) 9.4.1 device parameter test conditions min typ max unit i suppl y current (internal volta g e re g ulator enabled, see note 4 33 ma i dd su ly current (internal voltage regulator enabled , reg_en = l) see note 5 8.1 ma i supply current (reg_en = h, external 1.8 v supplied see note 4 31.5 ma i dd su ly current (reg _ en = h , external 1 . 8 v su lied to reg18) see note 5 6.6 ma i dd(ulp) supply current ? ultralow power mode (internal voltage regulator enabled, reg_en = l) ports disabled v dd = 1.8 v (internal) t a = 25 c 1.5 ma i dd(ulp) supply current ? ultralow power mode (internal voltage regulator disabled, reg_en = h, reg18 = 1.8 v) ports disabled v dd = 1.8 v (external) t a = 25 c 35 a v th power status threshold, cps input ? 400-k ? resistor ? 4.7 7.5 v v o tpbias output voltage at rated i o current 1.665 2.015 v i i input current (pc0 ? pc2 inputs) v dd = 3.6 v 5 a i pullup current (g rst input) v i = 1.5 v ? 90 ? 20 a i irst pullup current (g_rst input) v i = 0 v ? 90 ? 20 a ? measured at cable power side of resistor. notes: 4. transmit (all ports transmit, 100% bandwidth, s400), v dd = 3.3 v, t a = 25 c 5. idle (receive or transmit cycle start on the port), v dd = 3.3 v, t a = 25 c 9.4.2 driver parameter test conditions min max unit v od differential output voltage 56 ? , see figure 9 ? 1 172 265 mv i diff driver difference current, tpa+, tpa ? , tpb+, tpb ? drivers enabled, speed signaling off ? 1.05 ? 1.05 ? ma i sp200 common-mode speed signaling current, tpb+, tpb ? s200 speed signaling enabled ? 4.84 ? 2.53 ma i sp400 common-mode speed signaling current, tpb+, tpb ? s400 speed signaling enabled ? 12.4 ? 8.1 ma v off off state differential voltage drivers disabled, see figure 9 ? 1 20 mv ? limits defined as algebraic sum of tpa+ and tpa ? driver currents. limits also apply to tpb+ and tpb ? algebraic sum of driver currents. limits defined as absolute limit of each of tpb+ and tpb ? driver currents. tpax+ tpbx+ tpax ? tpbx ? 56 ? figure 9 ? 1. test load diagram
9 ? 5 9.4.3 receiver parameter test conditions min typ max unit z differential impedance drivers disabled 4 7 k ? z id differential impedance drivers disabled 4 pf z common mode impedance drivers disabled 20 k ? z ic common-mode impedance drivers disabled 24 pf v th-r receiver input threshold voltage drivers disabled ? 30 30 mv v th-cb cable bias detect threshold, tpbx cable inputs drivers disabled 0.6 1 v v th + positive arbitration comparator threshold voltage drivers disabled 89 168 mv v th ? negative arbitration comparator threshold voltage drivers disabled ? 168 ? 89 mv v th ? sp200 speed signal threshold tpbias ? tpa common mode voltage, drivers disabled 49 131 mv v th ? sp400 speed signal threshold tpbias ? tpa common mode voltage, drivers disabled 314 396 mv 9.5 thermal characteristics parameter test conditions min typ max unit 128-pdt r ja, high-k board 74.6 c/w 128-pdt r ja, low-k board board mounted, no air flow, jedec test board 101.3 c/w 128-pdt r jc ,, 18.7 c/w 9.6 switching characteristics for phy port interface parameter test conditions min typ max unit jitter, transmit between tpa and tpb 0.15 ns skew, transmit between tpa and tpb 0.1 ns t r tp differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns t f tp differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns 9.7 operating, timing, and switching characteristics of xi parameter min typ max unit v dd 3.0 3.3 3.6 v (pllv dd ) v ih high-level input voltage 0.63 v dd v v il low-level input voltage 0.33 v dd v input clock frequency 24.576 mhz input clock frequency tolerance <100 ppm input slew rate 0.2 4 v/ns input clock duty cycle 40% 60% 9.8 switching characteristics for pci interface ? parameter measured min typ max unit t su setup time before pclk ? 50% to 50% 7 ns t h hold time before pclk ? 50% to 50% 0 ns t val delay time, pclk to data valid ? 50% to 50% 2 11 ns ? these parameters are ensured by design.
9 ? 6 9.8.1 cardbus pc card clock specifications parameter min max unit t cyc cclk cycle time (see note 6) 30 ns t high cclk high time 12 ns t low cclk low time 12 ns ? cclk slew rate (see note 7) 1 4 v/ns notes: 6. in general, all cardbus pc card components must work with any clock frequency up to 33 mhz. the clock frequency may be changed at any time during the operation of the system so long as the clock edges remain clean (monotonic) and the minimum cycl e and high and low times are not violated. if the clock is stopped, it must be in a low state. a variance on this specification i s allowed for the cardbus pc card adapter which may operate the cardbus pc card interface at any single fixed frequency up to 33 mhz, and may enforce a policy of no frequency changes. 7. rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform (see figure 9 ? 2). 0.4 v cc, p-to-p (minimum) 0.325 v cc 0.4 v cc 0.475 v cc 0.2 v cc 0.6 v cc t low t high t cyc figure 9 ? 2. cardbus pc card clock waveform 9.8.2 3.3-v timing parameters min max unit t val cclk-to-signal-valid delay (see notes 8 and 9) 2 18 ns t on float-to-active delay (see note 8) 2 ns t off active-to-float delay (see note 8) 28 ns t su input set up time to cclk (see note 10) 7 ns t h input hold time from cclk (see note 10) 0 ns t rst reset active time after power stable (see note 11) 1 ms t rst-clk reset active time after cclk stable (see note 11) 100 clocks t rst-off reset-active-to-output-float delay (see notes 11 and 12) 40 ns t pulse cstschg remote wakeup pulse width (see note 13) 1 ms notes: 8. t val includes the time to propagate data from internal registers to the output buffer and drive the output to a valid level. minimu m t val is measured from cclk crossing v test to the signal crossing v ih on falling edges and v il on rising edges. maximum t val is measured from cclk crossing v test to the signal ? s last transition out of the threshold region (v il for falling edges, v ih for rising edges). 9. minimum times are specified with 0-pf equivalent load; maximum times are specified with 30-pf equivalent load. actual test capacitance may vary, but results must be correlated to these specifications. systems which exceed this capacitance, due to lon g traces between the socket and adaptor, must reduce the cclk frequency appropriately. 10. t su and t h are measured at v th for rising edges and v tl for falling edges. 11. crst is asserted asynchronously and negated synchronously with respect to cclk. cclk stable means that v cc is within tolerances and cclk is meeting specifications. 12. see pc card standard ? electrical specification for the cardbus pc card and adapter signals which must be in a high-impedance state. 13. this parameter only applies when signaling remote wakeup over the cstschg terminal. all other status change information must be signaled by asserting cstschg until the resultant interrupt is serviced.
10 ? 1 10 mechanical information the TSB43AB21A device is packaged in a 128-terminal pdt package. the following figure shows the mechanical dimensions for the pdt package. pdt (s-pqfp-g128) plastic quad flatpack 64 33 0,13 nom gage plane 0,25 0,45 0,75 seating plane 0,05 min 4087726/a 11/95 0,23 0,13 65 32 96 1 12,40 typ 128 97 sq sq 0,95 1,05 15,90 16,10 13,95 1,20 max 14,05 0,08 0,40 m 0,05 0 ? 5 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec mo-136
10 ? 2

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